Automatic Generation of Equivalent Architecture Model from Functional Specification

1
Automatic Generation of Equivalent Architecture
Model from Functional Specification

• Samar Abdi and Daniel Gajski
• Center for Embedded Computer Systems, UC Irvine
• http//www.cecs.uci.edu

2
Outline

• Motivation
• Related work
• Formal model representation
• Equivalence of system models
• Architecture model generation
• Experimental Results
• Conclusions and future work

3
Motivation

• Rising levels of abstraction
• Design complexity
• Verification complexity
• System level models
• Each needs verification
• Must retain properties
• Cannot compare independent models
• Goal
• Formalize models
• Stepwise refinement of models
• Ensure correct refinement

4
Possible Design Methodology
Evaluate
Specification Model
Designer Decisions
Architecture Refinement
Architecture model
Evaluate
Designer Decisions
Bus-Functional model
Evaluate
Cycle Accurate model
5
Related Work

• Formal methods in modeling
• Process Algebras
• Concurrent Sequential Processes (C.A.R. Hoare)
• Calculus of Communicating Systems (R. Milner)
• Harels StateCharts, PetriNets etc.
• Correct by construction synthesis
• High level synthesis (R. Camposano)
• Term rewriting
• Correct hardware synthesis (Arvind et al. at MIT)
• Our approach
• Simple formalism usable for system modeling
• Well defined model semantics
• Application to a system design methodology

6
Outline

• Motivation
• Related work
• Formal model representation
• Equivalence of system models
• Architecture model generation
• Experimental Results
• Conclusions and future work

7
Modeling Constructs
Vin
v

• Behaviors (computation)
• Identity behavior
• Channels (communication)
• Data flow
• Ports (unblocked)
• Channels (rendezvous)
• Control Flow
• Ordered
• Synchronized

b
e
v
Vout
8
Formal Model Representation

• Model
• lt objects, composition rules gt
• Objects
• Behaviors
• Channels
• Composition rules
• Hierarchy by grouping
• Control Flow
• Creates execution order
• Data Flow
• Through channels/ports

s1
1
v1
v1
c
b1
b2
1
s2
v2
1
b3
q1
1
b4
v3
1
t2
q1
t1
9
Execution Semantics

• Atomic actions
• Behavior execution
• Read , execute, write
• Channel semantics
• Sender
• Write data
• Send notification
• wait for ack
• Receiver
• Wait for notification
• read data
• send ack
• Model Execution
• Partially ordered trace

b.rd(Vin)
b.ex
b.wr(Vout)
10
Outline

• Motivation
• Related work
• Formal representation of system models
• Equivalence of system models
• Architecture model generation
• Experimental Results
• Conclusions and future work

11
Notion of Model Equivalence

• Model execution as a graph
• Partial order graph (POG)
• Nodes are actions of leaf behaviors
• Edges are dependencies
• Models with identical POGs are equivalent

start
b1.rd()
b2.rd()
b1.wr(v1)
b.ex
b2.ex
b2.rd(v1)
b2.wr(v2,v3)
b1.wr()
b3.rd(v2)
b3.ex
b3.wr()
b4.rd(v3)
b4.ex
b4.wr()
end
start
12
Functionality Preserving Transformations

• Expression exchange
• Forward substitution
• Flattening
• Transitivity
• Channel creation

13
Architecture Model Generation

• Create Parallel PEs
• Copy original hierarchy
• Modify leaf behaviors
• Add synchronization
• Route data flow

14
Proof of Correctness

• Algorithm Path
• Few big transformations
• Faster implementation
• Proof Path
• Several small transformations
• Slower implementation
• Algorithm path is a theorem !
• Proved by transformations

Specification
Model
Proof Path
Algorithm
T3
T2
Architecture
Model
T1
15
Experimental Results

• Architecture exploration performed for 3
  different configurations on a Voice Codec model
• New architecture models generated within seconds
• Manual effort estimated for 50 LOC per person-day
• Savings in simulation time
• Spec model simulates significantly faster
• Architecture model with 4 PEs runs almost twice
  as slow

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Conclusions and Future Work

• Contributions
• Equivalence notion using partial ordered traces
• Functionality preserving transformations of
  system level models
• Proof of correctness for refinement algorithm
• Only need to verify the specification model
• Significant reduction in model verification time
• Restrictions
• Limited support for exceptions and interrupts
• No canonical form yet ?
• Future Work
• Extend formalism to support more communication
  types
• Define transformations and proofs for
  communication and cycle accurate refinements