STATUS OF TRD PASA MASSTESTING

1
STATUS OF TRD PASA MASS-TESTING

• Hans Kristian Soltveit
• Ruprecht Karls Universität Heidelberg

2
OUTLINE

• Test setup
• Some TPC PASA measurement results
• Time schedule for the mass testing of TRD-PASA
• Proposal of tolerances

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AUTOMATIC WAFER TESTER
Microscope
Control area
Chuck, needle card, needle card adapter and wafer
Main PASA tester
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Needle card and needle card adapter
Needle card
Needle card adapter
Needles
Needles
Needle card adapter
Connection between needle card adapter and the
main PASA tester
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WAFER MAP
Created a wafer map One time
Coordinate settings One time, but
recheck
1275 dices
Surface screening For every
wafer
Removal of not fully processed chips One time
The error code is GO-NOGO
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MEASUREMENT DATA FOR TPC-PASA
Yield 96.4
(Eng.Run) The errors was mainly due to handling
effects

• Parameters tested
• Conversion gain
• Peaking time
• Base-line variation
• Power consumption

2400 chips tested
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MEASUREMENT DATA FOR TPC-PASA
Yield of working is here 98.2
Acceptance level
Baseline variation /-50 mV Peaking time/-
6 Gain tolerance /-5 With this contrains,
we got a Yield of nearly 90
36 200 chips is here tested
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Time schedule

• Start around the 14.Feb 2005 (ATLAS finished with
  the production). One known break of about two
  weeks in mid April due to the arrival of the
  BEETLE chip.
• 97 wafers with 1275 chip/wafer (A total of 123
  675 chips)
• One wafer take 14 hours to test (includes 4h of
  cleaning/re-installation)
• 97 wafers takes about 175 working days (8h) to
  test (includes 45 working days with
  cleaning/re-installation)
• An automatic cleaner would be desirable. Could
  use the tester on a 24 h basis. Supervised by a
  webcamera. PASA, BEETLE, OTIS and TRAP will save
  a lot of TIME and MANPOWER (cost 30000 euro).
  Delivery time about 6 weeks (Ralf Achenbach)
• Anticipated yield is somewhere between 90-100
  (TPC-PASA had 98.2 working chips, even 90
  after tight selection criteria /-6)
• Need 65 664 for 100 detector 10 spares
  (6500). Gives a total of 72 164 to be tested. If
  we have 90 yield must we test about 80 000 chips
  (63 wafers).
  Electronic assemble
  yield (MCM and readout board production) not
  included.
  Need
  16 needle cards 35 000 euro
• For a 60 solution 48 000 chips. 67 working
  days of testing. Need 10 needle cards 22 000
  euro

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PROPOSAL OF TOLERANCES

• Acceptable tolerances for Power consumption,
  base-line variation, peaking-time and conversion
  gain. This we will first know after the first
  tested wafers.
• Typical values we have seen from the first tested
  chips (several hundred)
• Power consumption 90 mA/chip - ?
• Baseline variation /- 50mV
• Peaking-time variation /-6 (110ns)
• Conversion gain /-5
• Do we want to test additional parameters?