Design of the IRAM FPU

1
Design of the IRAM FPU

• Ioannis Mavroidis
• maurog_at_cs.berkeley.edu
• IRAM retreat
• July 12-14, 2000

2
Features

• Executes MIPS IV ISA single-precision FP
  instructions
• Thirty-two 32-bit Floating Point Registers
• Two 32-bit Control Registers
• One 3-cycle (division takes 10 cycles) fully
  pipelined, nearly full IEEE-754 compliant,
  execution unit (from Albert Ma_at_MIT)
• Support for partial out-of-order execution (with
  the use of a reorder buffer) and precise
  exceptions
• 6-stage pipeline (R-X-X-X-CDB-WB)

3
Interface with Scalar Core

• The FPU is attached to the Scalar Core as a
  loosely-coupled coprocessor. Scalar core
  dispatches FP instructions to FPU using an
  interface that splits instructions into 5
  classes.

4
FPU Architecture
5
Current Functionality

• Executes all instructions (except division).
• A few modifications are needed to adapt to recent
  interface changes with the Scalar Core. Also some
  things about exceptions and division are still
  missing.
• Functionality verification.
• Used random test generator that generates/kills
  instructions at random and compares results from
  Verilog simulator against results from an ISA
  simulator (written in Perl).

6
Future Work

• Integrate execution datapath from MIT
• Can not compile it without the IBM libraries!
• Integrate it with MIPS Scalar Core
• Run FPU testsuite provided by MIPS
• Integrate with vector unit and run tests that use
  both coprocessors
• Synthesize, place and route