10 Gb/s PON FEC-Framing - PowerPoint PPT Presentation

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10 Gb/s PON FEC-Framing

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There are two parts to the FEC puzzle. Framing,' or how to arrange the bits. Algorithm,' or the actual math of FEC. This set of s concentrates on framing. FEC ... – PowerPoint PPT presentation

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Title: 10 Gb/s PON FEC-Framing


1
10 Gb/s PON FEC-Framing
  • Contributors names
  • Sept 2006

2
Introduction
  • Presentations in July seemed to demonstrate
    general consensus on
  • FEC is definitely needed for 10G
  • FEC should be at the lowest layer
  • There are two parts to the FEC puzzle
  • Framing, or how to arrange the bits
  • Algorithm, or the actual math of FEC
  • This set of slides concentrates on framing

3
FEC framing
  • FEC will be applied at the lowest layer
  • Below the 64b66b sub-layer
  • Right before the PMA
  • FEC sub-layer will be responsible for obtaining
    codeword lock, because without it, FEC is
    impossible
  • Frame lock must work with extensive errors
  • In the upstream, lock must work very fast
  • 64b66b sub-layer will be handed aligned data, so
    there is no need for its own framing system

4
FEC framing structure issues
  • There are several differently sized data objects
    in the 10G EPON technology that we should
    consider
  • 64b66b blocks, 6.4 ns long
  • MPCP time quanta, 16 ns long
  • FEC codeword, (yet to be determined)
  • The simplest and most efficient system will
  • Arrange objects so sizes are related by ratios of
    small integers
  • Result in a final line-rate that is a small
    integer ratio of the input MAC rate

5
64b66b and time quanta
  • The least common denominator of time quanta and
    64b66b blocks is 32 ns
  • 5 blocks
  • 2 time quanta
  • Regardless of FEC code choice, if we want to keep
    things neat, then time-quanta should always be
    specified in even numbers

6
RS code as an example
  • For this presentation, we will consider the tried
    and true RS(239,255) code (and shortened
    variants) as a example code
  • This gives us a concrete set of code constraints
    to work out the method of solution
  • This is not meant to favor RS over other codes
  • As the PMD analysis moves forward, the choice of
    FEC algorithm will get clearer
  • However, the basic ideas presented here will
    remain the same

7
Form of FEC codeword
  • A FEC codeword will contain three important items
  • Framing pattern
  • User data
  • FEC parity
  • In continuous mode systems, framing pattern is
    typically short, and state machine with long
    memory is used to lock onto codewords
  • In burst-mode systems, framing pattern is longer,
    to provide instant lock-on
  • This can occur once at the beginning of the
    frame, with no further framing structure required

8
Good codeword arrangements for 66b blocks
  • Maximum number of 66b blocks that fit is 28
  • 1848 bits payload
  • 40 bits synchronization
  • 128 bits parity
  • 252 total bytes 9/8 line rate
  • With an even number of quanta, 25 blocks fit
  • 1650 bits payload
  • 22 bits synchronization
  • 128 bits parity
  • 225 total bytes 9/8 line rate

9
Choice of 64b66b encoding
  • The 2 bit header in 64b66b is redundant, since
    FEC sub-layer will be aligning the data
  • Can reduce to 1 bit (the T-bit) to increase
    effciency
  • Sounds good, but redundant bits in the payload
    could be used for auxilliary alignment purpose,
    so sending 66b blocks is not useless

10
Good codeword arrangements for 65b blocks
  • Maximum number of 65b blocks that fit is 29
  • 1885 bits payload
  • 17 bits synchronization
  • 128 bits parity
  • 2030 total bits 35/32 line rate
  • With an even number of quanta, 25 blocks fit
  • 1625 bits payload
  • 22 bits synchronization
  • 128 bits parity
  • 1775 total bits 71/64 line rate

11
Downstream FEC synchronization
  • In the downstream, any of the above mentioned
    framing lengths would work
  • We would adjust the state machine parameters to
    obtain whatever lock probabilities we wanted
  • For reference, 264 was considered a good lock
    in the 66b system
  • 24 sync patterns will produce similar results

12
Upstream FEC synchronization
  • Two phases of synchronization
  • Initial lock requires a larger and
    error-resistant sequence that can reliably
    produce a unique autocorrelation signal
  • For reference, merely 20 bits is recommended for
    G-PON operating at 1e-4 raw BER
  • Maintenance is nearly redundant (protects against
    clock slips how frequent are they?) but
    probably will be included to retain clock
    frequency harmonization
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