The%20J%20Computer

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The J Computer

• Advay Mengle
• MIT 6.111, Spring 2007
• April 25, 2007

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The J Computer

• Executes Java ME-like bytecode in hardware
• Constraints (relatively) slow clock rate, not
  much memory
• Use Connected, Limited Device Configuration v1.0
• Downloads user-specified class files from PC over
  RS-232 connection
• Interfaces with hardware devices to allow user
  interaction

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System Architecture
Main General uP
SRAM
arbitrary backend
Specialized uP for Static Class 3
RS-232
Method Bus control and data
Specialized uP for Static Class 2
Specialized uP for Static Class 1
More processors if FPGA size allows
arbitrary backend
arbitrary backend
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System Architecture
RGB
Main General uP
SRAM
Overlay_Manager
VGA_Controller
x,y
ARGB, oue
Specialized uP for Static Graphics Class
N overlays
N overlays
N overlays
RS-232
pos, color
Method Bus control and data
Specialized uP for Static PS/2 Handler Class
Specialized uP for Static System Class
More processors if FPGA size allows
x,y
mouse_clock, mouse_data
ps2_frame
Mouse_Handler
scancode
Generic PS2_Handler
keybd_clock, keybd_data
Keybd_Handler
ps2_frame
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Executing HLLs in Software vs. in Hardware
Software VM
Native Processor
Java Source
Java Source
javac
javac
Compiled
Compiled
Java Bytecode
Java Bytecode
Verified Interpreted JIT-compiled
Executed
java (VM)?
µP
Native MC
Each bytecode can be one or more native
instructions
µP
Executed
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General Microprocessor Simplified
to/from SRAM
Memory_Manager
Bytecode Processing Variable length instructions
split into 8-bit cellsloading, parsing, flow
control
Class_Manager Parses class files
Object_Manager creates and modifies object
instances
RS_232_UART receives and transmits buffered
data to RS-232
to/from desktop
addr
bytecode_cell
init
Bytecode _Reader reads bytecode at PC
Jump _Control controls PC
Invoker calls static or instance methods
Method Bus
control
data
Boot controls boot-up
bytecode_cell
ready
jmp_pc
en
index
en
reset (to all)
SOP_Control setup control signals to all other
components
Bytecode _to_SOP translation
sop
raddr1,2
Reg_File 16 regs, 32 bits
rdata1,2
SOP (Simple OPeration) Processing 40-bit
instructions w/ 8-bit op-code, and either 4 8-bit
params or one 32-bit literal computation
ready
waddr, wen
wdata
ctl, addr
Stack Manager
ALU_32 computes arithmetic function of 2
32-bit integers
A, B
alu_op
data
Z
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General Microprocessor Simplified
to/from SRAM
addr, data, r/w
Memory_Manager
Class_Manager Parses class files
Object_Manager creates and modifies object
instances
RS_232_UART receives and transmits buffered
data to RS-232
to/from desktop
addr
bytecode_cell
init
Bytecode _Reader reads bytecode at PC
Jump _Control controls PC
Invoker calls static or instance methods
Method Bus
control
data
Boot controls boot-up
bytecode_cell
ready
jmp_pc
en
index
en
reset (to all)
SOP_Control setup control signals to all other
components
Bytecode _to_SOP maps one or more bytecode cells
to one or more SOPs
sop
raddr1,2
Reg_File 16 regs, 32 bits
rdata1,2
ready
waddr, wen
wdata
ctl, addr
Stack Manager
ALU_32 computes arithmetic function of 2
32-bit integers
A, B
alu_op
data
Z
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Bytecode-to-SOP translation
bc8
ready

• Most bytecodes can be directly translated into
  one or more constant SOPs (looked up in ROM)
• Others may generate custom SOPs dynamically

Bytecode _to_SOP
sop40
ready
bc
ready
FSM
addr
empty/full
sel
cust
ROM
FIFO gtgt
ready
sop40
sop_in
data
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Goals Challenges

• Final demo Write MIT Pong in Java
• The most complex bytecodes instanceof,
  invoke_virtual
• Need to traverse type trees
• Raise traps via SOP and write in Java, or
• Implement via in-BRAM data structures
• Gate count
• Can we fit 4 processors on a single FPGA?

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Questions?