Fundamental of Logic Design

1
Fundamental of Logic Design

• 1/15/09

2
Learning Objectives

• Review the basic concepts of logic circuits
• Variables and functions
• Boolean algebra
• Minterms and maxterms
• Logic gates
• Synthesis
• Create CMOS logic gates

3
Variables and Functions

• A function is defined as the dependency of
  output y on
• the n inputs (x1, x2, xn)
• The n inputs (x1, x2, xn) are variables
• The function of a combinational logic circuit
  can be expressed by
• a Boolean logic function
• For a Boolean logic function, output and inputs
  are binary,
• and the basic operators include AND, OR, NOT.

Example
4
Basic functions

• Summary of basic logic functions
• Inversion, AND, OR
• Can be used to implement logic function of any
  complexity

x
x
1
0
1
0
NOT
5
Logic gates

• The basic logic function (operation) can be
  implemented electronically with transistors,
  which is called a logic gate
• A logic gate has one or more inputs and one
  output
• schematics

x
x
1
1
x
x

x
x

x
x
1
2
1
2
x
x
2
2
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Truth Table
Representations of a logic function --
mathematic Algebra expression -- Truth Table --
Karnaugh map (next page)
Observations for an n-variable function 1) 2
rows in truth table 2) 2 different
n-variable functions totally
n
(2n)
4 different 1-variable functions f(x)0, f(x)1,
f(x)x, f(x)x 16 different 2-variable
functions 256 different 3-variable functions
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Karnaugh Map
8
x
x
1
2
x
3
00
01
11
10
0
0
1
1
0
f
x
x
x
x


1
3
2
3
1
0
0
1
1
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Boolean Algebra

• Axioms of Boolean Algebra
• 000, 010, 100, 111
• 000, 011, 101, 111
• If x0, then x1 if x1, then x0
• Single-Variable theorems
• X00, x1x, x0x, x11, xx1, xx0
• Multiple-Variable Properties
• Commutative, associative, distributive,
  absorption, combining, DeMorgans theorem

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Properties

• Commutative
• Associative
• Distributive
• Absorption
• Combining
• DeMorgans theorem

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Synthesis using basic logic gates

• Synthesis begin with a description of the
  desired behavior, and then generate a circuit
  that realizes this behavior.
• Example of synthesis

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Sum-of-Products

• Minterm any function can be expressed as the sum
  of some minterms.
• For a function of n variables, a product term in
  which each of the n variables appears once
• Variables either in uncomplemented or
  complemented form
• For a given row of a truth table, of 1,
  if 0
• Maxterm any function can be expressed as the
  product of some maxterms.
• For a function of n variables, a sum term in
  which each of the n variables appears once
• Variables either in uncomplemented or
  complemented form
• For a given row of a truth table, of 0,
  if 1

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Three-variable minterms and maxterms
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Sum-of-Products, Product-of-sums
POS
SOP
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Transistor as a switch

• Concept of switch
• Signals are assumed to have only 2 possible
  values(0, and 1)
• The basic element is a switch which has two
  states
• The switch state is controlled by an input
  variable x
• Switch is open if x0 closed if x1

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Implementation of Logic gates (1)

• Transistor switches

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Implementation of Logic gates (2)

• CMOS logic gates (as networks of transistors)

V
PUN
DD
T
1
V
V
x
f
T
2
PDN
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Implementation of Logic gates (3)

• PUN PMOS
• PDN NMOS
• Output Vf is selectively connected either to Vdd
  through PUN or to Gnd through PDN, depending on
  inputs

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Complex CMOS logic gate

• Example 3.1

For f1
For f0
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Procedures for complex logic gates

• Express a function so that all variables appear
  in their complemented form
• e.g.
• Derive the PUN based on
• Products ? transistors (or branches) in series
• Sums ? transistors (or branches) in parallel
• Derive a complemented function so that all
  variables appear in their uncomplemented form
• e. g.
• Derive the PDN based on
• Products ? transistors (or branches) in series
• Sums ? transistors (or branches) in parallel

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Exercise ?

• Create CMOS gate for function

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Analysis of complex CMOS gate

• Derive expression from circuit based on PUN
• Branches in parallel ? sums
• Branches in series ? products
• All variables in complemented form
• Derive PDN from PUN, or derive PUN from PDN
• For branches in parallel in PDN, there are
  branches in series in PUN vice versa.
• For branches in series in PDN, there are branches
  in parallel in PUN vice versa.

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Problem 3.9
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Homework

• Problem 3.1
• Problem 3.13