ADC System Architecture

1
ADC System Architecture

• LMS Adaptive Filter is designed to correct the
  errors from a high speed pipelined ADC.
• Analog accuracy problem is translated to DSP
  problem in this approach
• Error Signal
• ?(n)d(n)-X(n)TW(n)
• where d(n) is the correct/ideal value, W and X
  are vectors. X(n) is the input and W(n) is the
  tap values.
• Tap Update
• W(n1)W(n)2??(n)X(n)
• where ? is the step size . Step size determines
  the convergence time.
• LMS Output
• Y(n)W(n)TX(n)

2
2-1 MASH ?? Architecture

• ?? ADC specifications
• 14-bit accuracy (84.3dB Dynamic Range)
• ?1 Msample/sec

• Matching errors limit the additional dynamic
  range achievable with the extra stage

3
Voltage Scaled ??

• Applying voltage scaling to limit the output
  voltage swings of the integrators

DR100dB for M64
4
SQNR of 2-1 MASH ??

• Simulink simulation
• M64
• Peak SQNR95dB

5
Switched Capacitor Integrators

• Integrators are implemented with switched
  capacitors.
• Non-overlapping clocks are used to reduce
  switched charge injections.
• Bootstrapped clocks are employed at the input and
  the feedback switches to minimize signal
  dependent switch charge injection.
• The 1st integrator is shown below. The 2nd and
  3rd integrators are implemented using a similar
  structure.

6
Amplifier Design

• OTA architecture is a single stage gain boosted
  folded cascode
• High Gain, Gain ? (gmro)4
• High Speed
• The transistor sizes are limited by flicker noise
• The 2nd and 3rd are scaled versions of the 1st
  integrator to reduce power consumption

Gain
Vod
1st OTA
7
CMFB and Comparator

• Common Mode Feedback(CMFB)
• Switch capacitor common mode feedback circuit
• Common mode output is set at mid-rail

CMFB

• Comparator
• The performance of the modulator is relative
  insensitive to the comparator offset and
  hysteresis
• The effects of these impairments are noise
  shaped by the 2nd order modulator the same as the
  quantization noise.

Comparator
8
Clock Generation

• The operation of the modulation is controlled by
  non-overlapping clocks.
• To the first order, the MOS switch charge
  injection is canceled by the differential design.

9
Decimation Filter

• One bit raw codes from the ?? is decimated to 14
  bit codes using digital low pass FIR filter
• 2 stage decimation filter is the most suitable
  design considering hardware and filter transient
  response time