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Kanishka Lahiri

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Title: Kanishka Lahiri


1
Communication BasedPower Managementfor
Battery-Efficient System Design
  • Kanishka Lahiri
  • ESDAT Labs
  • Dept of ECE
  • UC San Diego

Sujit Dey ESDAT Labs Dept of ECE UC San Diego
Anand Raghunathan CC Research Labs NEC
USA Princeton, NJ
2
  • Communication Based Power Management
  • Exploits system-level communication architecture
  • Enables regulation of system power profile
  • Improves system battery efficiency
  • CBPM Advantages
  • Low hardware cost
  • System-level visibility
  • Dynamic control over system power profile
  • Battery-efficient systems

IEEE 802.11 MAC Processor
req
SPARC
addr
addr
grant
FIFO
FIFO
FIFO
addr
addr
addr
LLC
WEP
deq
full
Bus IF
full
full
deq
Bus IF
Bus IF
deq
SRAM
PLI
bridge
bus_2 arbiter
bus_1
Bus IF
Bus IF
Bus IF
Bus IF
Bus IF
Bus IF
bus_2
SPARC
SRAM
bus_1 arbiter
3
Outline
  • Battery Efficient System Design
  • Communication Based Power Management (CBPM)
  • Impact of CBPM on Battery Life
  • CBPM Enhanced Communication Architecture
  • CBPM Design Methodology
  • Design Example IEEE 802.11b MAC Processor
  • Experimental Results
  • Conclusions

4
Battery-Efficient System Design
  • Conventional low power techniques minimize total
    energy drawn by load system
  • For ideal energy sources
  • Minimizing energy Maximizing lifetime
  • For batteries (non-ideal energy sources)
  • Minimizing energy ? Maximizing lifetime
  • Lifetime depends on system power profile

5
Battery Discharge Characteristics
  • Rate Capacity Effects
  • Battery efficiency decreases at higher rates of
    discharge
  • Numerous battery models
  • Analytical, numerical, circuit based, stochastic
    etc.
  • Optimizing the system power profile can yield
    large improvements in battery efficiency

6
Communication Based Power ManagementBasic Concept
Using the system-level communication architecture
to dynamically regulate the system power profile
to suit battery discharge characteristics (e.g.,
rate capacity effects)
  • Request denied by CBPM policy

7
IEEE 802.11 MAC Processor Impact of CBPM on
Battery Life
Current Profile
Rated Ct.
Without CBPM
llc_mem
wep_mem
wep_init
Macro-state Ex. Traces
wep_comp
icv_mem
icv_comp
fcs_mem
fcs_comp
pli_mem
1 D.Panigrahi, C.Chiasserini, S.Dey, R.Rao,
K.Lahiri, Battery Life Estimation for Mobile
Embedded Systems, Intl. Conf. VLSI Design 2001
8
CBPM Enhanced Arbitration Algorithm
  • Communication architecture keeps track of
  • Set of current macro-states
  • Set of pending macro-states
  • CBPM enhanced architecture grants
    such that

C
S
  • Eqn (i) enforces selective executionof
    macro-states to minimize rated current violations
  • Eqn (ii) ensures minimal performance impact
  • Note CBPM policies cannot result in deadlock

9
CBPM Enhanced Communication Architecture
Standard Bus Protocol (e.g., Static
Priority, TDMA)
Power LUT
Fast Adders
Criticality LUT
Param- eters
Type II requests Represent macro-state
transition requests
Macro-state registers
CBPM Controller
Type I requests Represent conventional bus
access requests
Req4
Gnt4
Shared system bus
10
CBPM Design Methodology
11
Design of CBPM Policy
Macro-state Power LUT
Macro-state Criticality LUT
CBPM Policy
Parameters
  • CBPM may delay execution of certain macro-states,
    affecting macro-state criticalities

MS1
MS2
Macro-state Ex. Traces
MS3
MS4
MS5
12
Performance and Battery Analysis
13
Example IEEE 802.11 MAC Processor
HDR
WEP_ ENCRYPT
PLI
FCS
LLC
WEP_ INIT
To PHY
From Logical Link Control
Computed ICV
Transmit req/grant
MAC_CTRL
Functional View
ICV
Frame Data
To physical carrier sense
req
Architectural View
sparc_2 (FCS, MAC, HDR)
grant
f_queue1
addr
f_queue2
f_queue3
addr
addr
addr
addr
addr
LLC
WEP
deq
full
bus_2 I/F
To PHY
full
full
deq
From Logical Link Control
bus_1 I/F
bus_1 I/F
deq
bridge
mem_2
PLI
bus_2 arbiter
bus_1
bus_2 I/F
bus_2 I/F
bus_2 I/F
bus_1 I/F
bus_1 I/F
bus_1 I/F
bus_2
sparc_1 (ICV)
mem_1
bus_1 arbiter
K.Lahiri, A.Raghunathan, S.Dey,
Battery-Efficient Architecture for an 802.11 MAC
Processor Intl.Conf. on Communications, (ICC)
2002.
14
Experimental Methodology
  • IEEE 802.11 MAC processor implemented in Polis
    HW/SW Co-design environment
  • MAC processor enhanced with CBPM functionality
  • CBPM enhanced MAC processor evaluated with actual
    802.11 LAN traffic
  • HW/SW Co-simulation for performance measurements
  • Co-simulation based power profiling (Lajolo et
    al, DATE 2000)
  • Stochastic model of Li-ion battery (Panigrahi et
    al, VLSI 2001)

15
Comparison of Battery Discharge
300
300
250
250
200
200
Current (mA)
Current (mA)
Rated Current
Rated Ct.
Rated Ct.
150
Rated Current
150
100
100
50
50
0
Without CBPM
With CBPM
0
0
20
40
60
80
0
20
40
60
80
100
120
time (ms)
time (ms)
Battery state
Battery state
Time
Time
  • Original IEEE 802.11 MAC processor
  • Inefficient battery discharge
  • CBPM enhanced IEEE 802.11 MAC processor
  • Battery capacity improvement of 46

16
Battery Life/Performance Trade-off
  • Workload
  • 1.5 minutes of streaming video (4818 MAC frames)
  • Battery capacity, lifetime, data rate measured
    under 8 CBPM policy configurations.
  • Different settings of Pmax parameter
  • Substantial improvements in battery efficiency
  • Battery Capacity improvements up to 1.46x
  • Battery Lifetime improvements up to 3.18x
  • Configuration of CBPM enables flexible trade
    offbetween battery life and performance.

17
Comparison w/other Power Management Techniques
  • MAC Processor battery capacity/performancetrade-o
    ff under
  • Clock Frequency Scaling
  • Communication Based Power Management

260
240
CBPM
220
Original Architecture
200
Battery Capacity (mAh)
180
160
Freq Scaling
140
120
100
200
220
240
260
280
300
Data Rate (Kbps)
  • System clock frequency scaling can lead to
    anomalies
  • CBPM benefits are over and above idle shut down
    based DPM
  • CBPM results in superior trade-off characteristics

18
Hardware Implementation
  • Priority based arbiter enhanced with CBPM
    functionality
  • Synthesized (Synopsys Design Compiler), mapped to
    UMC 0.18um Cu library
  • Area results
  • 15104 sq.um
  • 56 increase over original arbiter
  • Less than 0.5 overhead at system level
  • Delay for Type II arbitration measured to be 4 ns
  • Max clock frequency 250 Mhz
  • Can be improved using multi-cycle arbitration for
    more complex, less frequent CBPM arbitrations

19
Conclusions
  • Communication Based Power Management
  • System-level communication architecture regulates
    power consumption
  • Dynamic regulatory control over system power
    profile
  • Suitable methodology for battery efficient system
    design
  • CBPM based architectures
  • Enable significant improvements to battery life,
    over and above what can be achieved by
    conventional power management
  • Can be statically or dynamically configuredto
    trade off performance for battery life
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