EEE 361 Digital Design and HDL Modeling

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EEE 361Digital Design and HDL Modeling

• Timing of Synchronous Sequential Circuits
• Chapter 6 M. M. Mano, C. K. Kime, Logic and
  Computer Design Fundamentals

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Quick Review
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Outline

• Timing of synchronous sequential circuits
• Determination of the maximum clock frequency
• Logic transformation to maximize clock frequency

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Outline 2
Code in VHDL
Analyze
Simulate
N
Expected behaviour?
Synthesize
Y
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Determining the minimum clock period

• Tp Period ( the inverse of the frequency
  of the system clock C.
• Tslack Slack time is the extra time allowed
  in a clock period beyond that required
  by the logic path.
• Tpd,FF Propogation delay of a flip-flop.
• Tpd,Comb Delay due to the combinational logic.
• Ts The setup time. It is the time during
  which the input D of the flip- flop must be
  stable before the rising edge of the clock

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Determining the minimum clock period

• For a pair of flip-flops that are connected in a
  logical path
• For any combinational logic that exists between
  the output of the first flip-flop and the input
  of the second flip-flop we have Tp Tslack
  (Tpd,FF Tpd,Comb Ts)
• For all of the paths through the combinational
  logic, we must have Tslack 0. Therefore,
• Tp Tpd,FF Tpd,Comb Ts
• By considering all of the possible pairs of
  flip-flops in a circuit, the value of the clock
  must satisfy
• Tp Tp minimale
• where Tp minimale Max (Tpd,FF
  Tpd,Comb Ts )

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Example

• Suppose that we have a logic circuit that
  contains two identical flip-flops, and that
• Tp 1.5 ns
• Tpd,FF 0.2 ns
• Tpd,Comb 1.3 ns (the longest path in the
  combinational logic)
• Ts 0.1 ns
• Can this circuit function correctly with this
  clock?

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Example

• Answer
• We know that Tp Tslack (Tpd,FF Tpd,Comb
  Ts)
• Using the values above, we determine that
• Tslack - 0.1 ns
• We must always have Tslack ? 0. Therefore the
  answer is NO. ,
• For Tslack 0 , then
• Tp (Tpd,FF Tpd,Comb Ts) 1.6 ns
• and the function would function properly with Tp
  1.6 ns

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TSetup and THold for a flip-flop

• Fig 1.2. shows the setup time Ts and the hold
  time Th for the input signal relative to the
  rising edge of the clock signal for the D
  flip-flop in Fig 1.1. 
• Ts  The input D must be present at the input of
  the D flip-flop and must remain stable ( ie. not
  change value ) for at least Ts time units before
  the rising edge of the clock.  
• Th  The input D must be present at the input of
  the D flip-flop and must remain stable ( ie. not
  change value ) for at least Th time units after
  the rising edge of the clock.  

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Example for TSetup et THold

• Given that
• Ts 2 ns
• Th 1 ns
• Tpd,logic gate 1 ns

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Example for TSetup et THold

• Therefore
• D must be stable from 4 ns. before to until 1
  ns. before the rising edge of the clock.
• EN must be stable from 3 ns. before to 0 ns.
  before the rising edge of the clock
• If Tpd,logic gate is in the range 0.2 ns, 1.5
  ns, then
• D must be stable from 5 ns. before the rising
  edge of the clock to 0.6 ns. after the rising
  edge of the clock.
• EN must be stable from 3.5 ns. before the rising
  edge of the clock to 0.8 ns. after the rising
  edge of the clock.

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Minimizing the clock period

• Given the following circuit
• To minimize the clock period, we can apply the
  following transformation ( in either direction )
• After the transformation, we get

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• Questions?