A New Interlock Design for the TESLA RF System

1
A new Interlock Design for the TESLA RF System
H. Leich1, A. Kretzschmann1, S. Choroba2, T.
Grevsmühl2, N. Heidbrook2, J. Kahl2, 1(DESY
Zeuthen) 2(DESY Hamburg)

• The Problem
• The Interlock Architecture
• Implementation
• Status of the Project

2
Main Task of the Interlock Sytem
--gt to prevent any damage from the cost expensive
components of the RF station --gt also to prevent
any damage from other environment
Sources of Interlock Error Signals

• hard component failures (non-reversible hardware
  malfunction)
• --gt broken cable or damaged contact, dead sensor,
  ...
• soft errors (e.g. sparks in the klystron or wave
  guide system,
• temperature above a threshold, ...)
• error conditions caused by transient noise from
  the RF station itself

3
Interlock Subsystems
PITZ
Control system
Clear, Clock, Dout
Klystron interlock
Din
safety person IL o.k.
RF- leak 12
Person interlock
enable Klystron 12
12 gun signals separate
Low level RF
Clock...
all input signals internal states output
signals masks to BIS
all input signals internal states output signals
enable magnets 1 2
laser pulse length laser rep. Rate enable
RF enable alig.laser
enable BIS 12
enable shutter1 12
enable RF
Magnets
Beam inhibit system
Laser interlock
reset gun interlock
solenoid supply o.k.
Gun IL o.k.
laser shutter
Gun interlock
PM Gun fast
ADCs
9 analog signals
Profibus
4
Architecture of the existing Interlock
Strictly digital hierarchical Interlock
Process Analysis
Output to Process
Analog Process Input
Digital Process Input
Analog Output
Digital Output
Adapter Unit
Adapter Unit
Sensor
Sensor
Klystron, RF Station
5
Klystron Interlock Inputs

• Digital Inputs
• - Oil levels
• - Cooling water flow
• - Vacuum pump current
• Analog Inputs
• - Oil temperature
• - Cooling water temperature
• - Heater current
• - Solenoid current
• - SF6 gas pressure

6
Klystron Interlock Inputs / Outputs

• Preprocessed Inputs
• - Person interlock o.k
• - RF leakage detector
• - Modulator ready
• - Gun interlock o.k.
• - RF system ready
• Interlock Outputs
• - Modulator on
• - Heater power supply on
• - Solenoid power supply on
• - RF enable

7
Response Times

• Ultra Fast (UF) Rt lt 1 µs
• Fast (F) Rt 1 ... 5 µs
• Slow (SL) Rt gt 5 µs
• --gt Actual implementation only SL and F
• --gt ca. 40 signals to process

8
Overview over the new Interlock Design
Master Control System
Predefined Curve Data
Component Characteristics
Measured Characteristic
Interlock Logic implemented based on a
Microcontroller (Processor Core)
User programmable ASIC (FPGA)
Time discrete digital data
Analog/Digital Process Output
Digital Process Input
Analog Process Input
Sensor
Adapter Unit
Sensor
Klystron, RF Station
9
The Implementation
Implementation Constraints

• combine Control Interlock Functions into only
  one crate per RF-station
• perform communication between modules via
  backplane
• ( no extra cable for communication)
• process-I/O with no cables to the front side of
  the crate all cables from rear
• site
• use a standard with stable, fast enough easy
  to implement bus interface
• use a standard that gives flexibility at the
  level of system integration
• ( definition of backplane-ressources standard
  bus, user defined bus, )
• use a standard that saves investment over longer
  time scale
• use a standard to have the option to buy
  commercial available products
• (CPUs, DAQ components, piggy pack, e.g. IP
  modules, ...)
• use a standard that offers the option of
  additional boardspace
• (rear transition option)

limited space in TESLA-tunnel
Other, DESY defined constraints
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Implementation Details
DESY decision Use a VME64x system - VME64x
introduces 5 row (160 pins) connectors J1/J2 and
an optional 95pin-connector J0
415 pins Total 210 pins VME System 205
pins User Defined

• gt enough pin resources per slot and per
  backplane to build a compact interlock/control
  system
• VME is a stable, fast enough and easy to
  implement bus and instrumentation system
• mixed use of VME and VME64x devices possible
• rear transition board option
• easy system integration

DESY 205 pins User Defined 64 pins per slot
used for rear transition 141 pins across the
backplane to implement a fast user bus
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DESY-VME64x-Backplane ( slot-pin configuration
)
c
z
d
a
b
1
J1
32
1
a
e
c
b
d
J0
19
z
a
c
1
b
d
J2
per Slot
per Slot
32
Rear I/O Connections 64 pins
VME64x Standard
12
Interlock / Control Crate
Interlock Master / Sequencer
VME-CPU (VME-Controller)
Up to 16 I/O-Modules
HD
Profibus
Reserve
Control- / Monitoring
Interlock
13
Interlock / Control Crate (Side view)
Front Boards (160 mm) VMEbus Interface Interlock
/ Master Logic I/O resources User Bus Interface

• Rear Boards (160 mm)
• Rear Transition Signals
• Additional I/O-functions
• Signal conditioning

VME64x Backplane, 160pin-J1/J2, 95pin-J0 (with
J0 full J2-pins rows z,d bussed)
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Structure of the DESY User Defined Bus Sytem
Master / Sequencer 110 lines connected 22
Time-Mux-Bus 34 Control-Bus 16 Event-Bus 2
BusInit, BusClock 4 Reserve BusControl 32 Reserve
(bi-directional) (all lines GTL)
BusInit, BusClock
I/O-Module other Modules
Time-Multiplex-Bus
Control-Bus
Event-Bus
Reserve
31 lines spare at backplane for free use by other
(future) components / systems
Event-Bus and/or Reserve could be defined as
LAM (Emergency Line) for Interlock Signals with
very high priority
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Bus Timing

• Time Mux Bus

BCLK
Init_l
ADDR
3
2
1
0
Data
D(0)
D(2)
D(1)
D(0)
D(3)

• Control Bus

BCLK
STRB_l
WE_l
ADDRi
ADDRj
Address
Data Out
Data In
Data

• Event Bus

BCLK
SRVRQ_l
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Architecture of the Interlock Master / Sequencer
AM5..0, AS, DS1..0, Write, LWord, Iack,
IackIn
ACEX EP1K100 FC484
VME Access Control VME Interrupt Control
ABT2244
Dtack, Berr, IRQ7..4, IackOut
Req
Ack
Req
Ack
Ack
F38
ROM Access Arbiter Address Mux
Req
Ctrl Out Ctrl In
ABT162244
Data Bus DB15..0
Data Bus
VME Bus
Interlock I/O Boards
ROM 512 x 16
Interlock Logic (Sequencer/ Controller)
Address Bus A23..1
Address Bus
Ack
ABT2244
DPM Access Control
Req
Data Out Data In
Data Mux
CE
CS
WE
Address Mux
Nonvolatile SRAM 64K x 16 (4 x U634H256CSK25)
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Other Modules under Construction

• Digital Input Module
• Digital Output normal
• Digital Output ultrafast
• Analog IO fast
• Digital IO LWL (Rear Module)

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Status of the Project

• Architecture definition ? finished
• Backplane design manufacturing ? finished
• Master/Sequencer design ? finished/assembled/test
  ed
• I/O Module design ? DigiIn assembled, not yet
  tested
• DigiOut, DigiOutFast layout process
• Analog I/O design not yet finished
• Digital IO LWL not yet designed
• Firmware design ? ongoing

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Existing RF Interlock System
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VME64x-Crate with DESY VME64x Backplane
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Interlock Master / Sequencer Module