Lab tests of 3DSTC detectors fabricated at ITCirst

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Lab tests of 3D-STC detectors fabricated at
ITC-irst

• David Pennicard - University of Glasgow
• R. Bates, C. Parkes, L. Cunningham, V. OShea, F.
  Docherty, A. Saavedra , A. Blue (University of
  Glasgow),
• V. Wright (Diamond Light Source)
• S. Ronchin, M. Boscardin, C. Piemonte, A. Pozza
  and N. Zorzi (ITC-irst, Microsystems Division)
• G. Pellegrini (CNM, Barcelona)

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Outline

• Introduction 3D-stc (single-type column) devices
  received from ITC-irst
• Simulation of 3D-stc devices
• I-V tests of planar and 3D-stc devices
• C-V tests of planar and 3D-stc devices (work in
  progress)
• MIPs testing (work in progress)
• Future work

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Devices from ITC-irst

• 2 samples on FZ and MCz
• p- substrates
• n columns
• p implant on backside
• Each sample has
• 4mm2 planar test diode
• 5 3D-stc arrays
• Other planar and 3D test structures

Images from S. Ronchin et al Fabrication of 3D
detectors with columnar electrodes of the same
doping type presented at PSD 07 Liverpool
september 12 16 2005 to appear in Nucl. Instr.
Meth. A, 2006.
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Substrates
1 out of 5 devices has 100µm pitch

• Ideally, columns should pass most of the way
  through the device
• In these 3D-stc samples, the column depth is
  small compared to the substrate thickness
• As a result, their behaviour will differ from
  ideal 3D-stc devices

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Simulation of 3D-stc devices

• Simulations were produced using ISE-TCAD
• Dimensions match devices produced by ITC-irst
• Bulk doping concentration was obtained from the
  quoted minimum resistivity of the Float Zone
  silicon used by IRST
• Bulk doping may be lower in the real devices

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Simulation of 3D-stc devices

• For this first iteration, the column structure
  was simplified to speed up the simulation process

• IRST devices
• Columns etched away
• Interior of columns doped by phosphorus diffusion
• Hollow columns are then passivated
• P-stop is used to prevent the columns being
  shorted together
• Simulated devices
• Columns are not hollow
• Columns consist of phosphorus-doped silicon
• No p-stop is used (effects of oxide charge are
  not being simulated)

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Depletion of 3D-stc devices
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Streamtraces in 3D-stc devices
Electrons drift laterally to nearest
electrode Holes drift to point at centre of
cell, then towards the back plane More
complicated behaviour near bottom of electrodes
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Streamtraces in 3D-stc devices
Data taken from Z75µm slice (i.e. half of column
depth)
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Lateral electric field
Lateral field is produced by space-charge between
n electrodes Once region between electrodes is
depleted, increasing the bias does not increase
the lateral field
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Vertical electric field
Z-component of electric field in this region
causes holes to drift to back plane Field is
relatively low
Roughness of curve due to wider spacing of mesh
points in Z-direction
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Vertical electric field
Below 11V, this region is not depleted Above 11V,
the vertical field increases with applied bias
Roughness of curve due to wider spacing of mesh
points in Z-direction
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MIPs simulation (in progress)

• Currently simulating charge collection when a MIP
  passes through the device

Current read out from nearest electrode
MIP arrives at (55um, 55um)
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Experimental work
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Planar test diodes

• 4mm2 n-p diodes
• Guard ring
• 2 p-stop rings

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I-V results planar test diodes
Breakdown MCz 180V FZ 270V
Ileak at 40V MCz 3.1nA/cm2 FZ 3.9nA/cm2
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I-V results planar test diodes
Reverse current saturates around
0.15V (Generation current then rises slowly as
depletion region widens)
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3D-stc devices from ITC-irst

• 10 10 array of n columns, connected together
• Columns 10µm diameter, 150µm depth
• Guard ring with either 38 or 44 columns
• 5 arrays with different configurations
• Different width and layout of p-stop
• 4 arrays with 80 µm pitch between electrodes, one
  100 µm pitch

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3D-stc devices from ITC-irst
Typical 3D-stc array (each of the 5 arrays is
different)
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I-V results 3D-stc devices
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I-V results 3D-stc devices
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I-V results 3D-stc devices
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I-V results 3D-stc devices
MCz samples have higher current at large biases
MCz devices have lower current below 70V
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I-V results 3D-stc devices
3d1 samples with no p-stop between guard ring and
electrode array break down
3d4 samples with larger pitch (100µm) show low
current
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I-V results 3D-stc devices low bias
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I-V results 3D-stc devices low bias
FZ 4V
Leakage current increases more rapidly with
voltage at low bias
MCz 9V
Associated voltages comparable to voltage
required to deplete between electrodes in
simulation
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I-V results 3D-stc guard rings
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I-V results 3D-stc guard rings
Guard rings breakdown MCz 150-190V FZ gt 190V
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I-V results 3D-stc guard rings
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I-V results 3D-stc devices
Increase in current around 25V (FZ) or 45V (MCz)
Guard ring current at 15V Minimum 70pA Maximum
270pA
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C-V tests (work in progress)

• Glasgow has just installed a new Cascade
  Microtech probe station
• Allows temperature and humidity control,
  electrostatic shielding, more reliable
  calibration etc.
• Also takes 12 inch wafers
• The samples will be tested once the station is
  ready to use

• Previously, CV tests were made
• with an older probe station, but
• Measurements were not temperature
• controlled, and capacitance values
• reached the lower limits of what the
• meter could measure (e.g. approaching 1.5pF for
  the 3D arrays at high biases)
• Results had poor repeatability, particularly at
  higher biases

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MIPs (work in progress)

• Have mounted samples on ceramic chip holders
• Ready to begin testing MIP charge collection
• Strontium-90 2.283MeV source

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Future work Ion Beam Microprobe

• University of Surrey
• Ion-beam induced charge (IBIC) microscopy
• Maps charge collection efficiency with position
• Uses a 1µm resolution, 3MeV proton beam
• Range of 3MeV beam in silicon is approximately
  100µm
• Not full depth of device, but well capable of
  mapping CCE between the electrodes

Images from Characterisation of charge transport
in compound semiconductor detectors, P.J. Sellin
et al, Radiation Imaging Group, Department of
Physics ,University of Surrey. rd50.web.cern.ch/RD
50/1st-workshop/talks/2A-RD50-1-Paul-Sellin.pdf
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Conclusions

• Simulations have shown
• that these early 3D-stc devices will experience
  full lateral depletion between the electrodes at
  10V followed by planar-like depletion towards
  the backplane
• how the electric field varies throughout the
  device and how this will affect the drift of
  charge carriers
• I-V measurements show
• leakage current varies with substrate type and
  device configuration
• e.g. bulk leakage current at 40V varies from 0.24
  to 0.76pA per column
• guard ring breakdown occurs starting at 150V
• Work is continuing on improved C-V measurements
  and charge collection using MIPs
• IBIC microscopy will allow mapping of charge
  collection with position

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Devices from ITC-irst
3D-stc arrays
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3D-stc devices from ITC-irst
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Simulation of 3D-stc devices
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Depletion of 3D-stc devices

• Depletion regions grow outwards from the n-p
  junctions around the columns
• At low voltages, the depletion regions grow
  cylindrically around the columns
• At 7V, the depletion regions of adjacent columns
  meet
• At 11V, the entire region between the electrodes
  is depleted
• At higher voltages, the depletion region grows
  downwards, much like in a planar diode

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Lateral electric field
Electric field strength is more than an order of
magnitude smaller in this region
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Lateral electric field
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Variation in lateral field with depth
Lateral electric field increases at base of column
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MIPs simulation
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11
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7
1
2
3
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MIPs simulation
e-
h
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Early CV simulation
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Early CV simulation
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I-V results 3D-stc devices
MCz devices have lower current below 70V
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I-V results 3D-stc devices
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C-V results 3D-stc devices
C levels out at 1.5pF for 100-column array 15fF
per column 230 pF/cm2 NB dubious results
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C-V results 3D-stc devices