Vincenne A07s 8Bit ADC Aug 7, 2003

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Vincenne A07s 8-Bit ADCAug 7, 2003

• Mark Burns
• Texas Instruments, Inc.
• Dallas Tx
• 972-480-3891
• mburns_at_ti.com

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Vincenne A07s 8-Bit GPADC Evolution
ACT5_LT 10-Bit ADC in A07
MIH DIE9 10-Bit ADC, A07 Servo Test Mode changed
to use voltage output, not current output to
control integrator Redesigned digital controller
to allow VHDL replacement if desired. Timing set
by delay elements to be identical in both Normal
Mode and Servo Test Mode. Reduction in area by
use of VMID holding caps as dummy caps.
Vincenne P3E 8-Bit ADC, A12 Lessons Learned Servo
Test Mode DC Offset Fix (500u x 400u)
Vincenne2 A07s Lessons Learned from P3E combined
with 8-bit version of 10-bit MIH DIE9 digital
controller, including servo test mode Herta A07
8-bit ADC analog block and 16-input GPMUX
modified to 14 inputs and split up into sections
as with Vincenne P3E Version (500u x 225u)
Herta A07 8-Bit ADC, A07 No Servo Test Mode
(analog section only) Digital controller for
Herta A07 is combined with other VHDL logic -
will reuse only the analog section for Vincenne
A07
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Review Charge Redistribution 8-Bit ADC
C 2.54 pF
VDD / 2
COMPO
Sampling Phase
390 W
VDD / 2
VDD
Vin
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Review Charge Redistribution 8-Bit ADC
C 2.54 pF
Hold Phase / MSB Comparison
VDD / 2
COMPO
VDD / 2
VDD
Vin
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Review Charge Redistribution 8-Bit ADC
C 2.54 pF
D6-D0 Comparisons (Sucessive Approximation)
VDD / 2
COMPO
VDD / 2
VDD
Vin
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Vincenne P3 8-Bit ADC
Vincenne P3 capacitor array is a 3/5 architecture
with a coupling cap
C 2.54 pF
VDD / 2
COMPO
C32/15
C/2
C/4
C
C/2
C/4
C/8
C/16
C/16
C/8
VDD / 2
VDD
Vin
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Herta A07 8-Bit ADC
Herta A07 analog section uses a 4/4 architecture
- will use this on Vincenne A07 BUT...
C 2.96 pF
VDD / 2
COMPO
C
C/2
C/4
C/16
C/2
C/4
C/8
C/16
0
C/8
VDD / 2
VDD
Vin
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Vincenne P3 uses a terminating cap of C/16, and a
non-unit coupling cap. This gives a 254-255 code
edge at VDD - 1 lsb. Herta uses no terminating
cap and a unit coupling cap, which gives 254-255
code edge at VDD. Vincenne A07 will use the
Herta scheme to avoid the non-unit coupling
capacitor (Improves DNL!!!).
C 2.96 pF
VDD / 2
COMPO
C
C/2
C/4
C/16
C/2
C/4
C/8
C/16
0
C/8
VDD / 2
VDD
Vin
Vincenne A07 8-Bit ADC
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Single Conversion Simulation

• Test Conditions
• ADCCLK 1 MHz
• AVDD DVDD 2.75 V
• 20 us conversion rate to second start signal
  (checking ability of controller to start another
  conversion)
• GPA0 conversion
• GPA0 1.0 V, Output Code 0101 1100
• All Other Channels 0 V
• Switch Control Timing
• Input voltage is sampled for 8 clock cycles
• VMID voltage disconnected and Comparator AC
  coupled 20 ns after rising ADCCLK edge (This
  reduces DC offset)
• 8ns later, S7 is switched
• 8ns after S7 is switched, S6-S0 are switched to
  VREFN (0V) and SAR begins

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Single Conversion on GPA0, Input 1.0V
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ADC Sample Timing
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Supply Currents

• AVDD Supply Currents
• Current surges gt 2.3 mA, but the surges are less
  than 1 ns wide
• DC Current averages approx. 265 uA for 16 clock
  cycles (16 us)
• DC Current settles to near 0 uA DC remaining
  clock cycles (84 us)
• Average IDDA 265 uA x (16 us / 100 us) 42
  uA
• DVDD Supply Currents
• Main spike during sampling period, 80ns by 250 uA
  - 0.2 uA average over 100us period
• Total average current
• 42.2 uA (plus 5 uA bias current for a total of
  47.2 uA) with continuous conversions every 100 us
• Previous (P3B) design pulled 110 uA under same
  conditions
• Power down currents lt 8 nA

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Supply Currents (IDDD, IDDA)
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Mux Tests, Clipping Ckts, Full Scale, Xtalk

• ADCCLK 1 MHz, AVDD DVDD 2.75 V, 20 us conv.
• FS/-FS test (and MUX functionality)
• GPA0 10 mV Code 0000 0000
• GPA1 13 mV Code 0000 0001
• GPA12 2.748 V Code 1111 1110
• GPA13 2.752 V Code 1111 1111
• Residual channel/channel crosstalk
• GPA5 10 mV (via 50 KW) Code 0000 0000
• GPA6 2.748V (no series resistance) Code 1111
  1110
• GPA7 10 mV (via 50 KW) Code 0000 0000
• Other Mux Functionality
• GPA2 1.2 V Code 0110 1111
• GPA3 1.3 V Code 0111 1000
• GPA4 1.4 V Code 1000 0001
• DCIO 1.8 VDC Code 1010 0110
• IMEAS 1.9 VDC Code 1011 0000
• VMEAS 2.0 VDC Code 1011 1001
• BDATA 2.7 (Checks Clipping Ckt) Code 1111 1010

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Multiple Conversions on Channels 0-7
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DAC INL and DNL Definition

• Integral non-linearity (INL) measures deviation
  from best-fit line (or endpoint line or abs.
  line)
• Differential non-linearity (DNL) measures
  consistency of step size
• VERY TIME CONSUMING TEST!!!

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Linear Ramp Histogram

• Code width is proportional to number of hits at
  each code (typically requires gt16 hits per code)

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Traditional Servo Technique

• External servo circuit automates the search
  process to find each code edge

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Test Mode Sampling Phase One Clock Period
C 2.54 pF
VDD / 2
COMPO
390 W
VDD / 2
VDD
Servo Input
Vin
Vincenne P3E Servo Test Mode
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Test Mode Compare Phase One Clock Period Skips
SAR Process, Saving Much Test Time
C
VDD / 2
COMPO
VDD / 2
VDD
Vin
Target Value Written to SC0-SC7 Via ADCIOlt70gt
Vincenne P3E Servo Test Mode
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Servo Test Mode Vincenne P3E
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P3E Servo Test Mode INL Curve
Histogram Test Method 256 hits per code, 1.3 sec
collection time.
Servo Test Mode 30 msec collection
time. Repeatability/resolution far better.
Correlation fairly good but needs work.
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P3E Servo Test Mode DNL Curve
Histogram Test Method 256 hits per code, 1.3 sec
collection time.
Servo Test Mode 30 msec collection
time. Repeatability/resolution far better.
Histogram data too noisy to judge correlation!
Coupling cap mismatch clearly visible at 0.1 LSB.
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Vincenne A07s Eliminates Current Source and
Fast/Slow Select
100 KW
0.1 mF
DV2IDT/C DT2 us, C100 nF, I(VDD/2)/100K,
DV550 uV
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Vincenne A07s Servo Test Mode
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Servo Test Mode Timing Comparison