FIFO introduction

1
FIFO introduction
2
The function of the FIFO

• Data width converter
• IP may use different data width. Data width
  converter can be integrate into FIFO easily
  without performance lost.
• Synchronize different data rate IP
• IP may have different data rate. Without FIFO it
  is impossible to connect them together.
• Input and output FSM
• IP may have its own input and output behavior.
  We can integrate the FSM into the FIFO.

3
The primitive signals - FIFO

1. CLK
2. RESETN
3. DATAIN
4. DATAOUT
5. READ or IP_LOAD
6. WRITE
7. EMPTY
8. FULL
9. FIFO_STOP
10. FIFO_RM_FULL
11. FIFO_WM_FULL

4
The primitive signals - GLOBAL

1. PIN_VCC
2. PIN_GND
3. ENABLE

5
FIFO signal introduction- READ or IP_LOAD

• READ or IP_LOAD
• READ signal means that the IP is active. The IP
  will tell the FIFO when to send the new data.
• IP_LOAD signal means that the IP is passive. The
  IP execute on fixed cycles. The FIFO will send
  the IP_LOAD signal to tell the IP new data is
  ready.

6
FIFO signal introduction- FIFO_STOP

• FIFO_STOP
• FIFO_STOP signal in the IP is used to indicate
  that when the IP should send the FIFO_RM_FULL
  signals.The FIFO_STOP value must be at least the
  pipeline depth of the previous IP. Otherwise,
  there will be buffer-overflow.

7
FIFO signal introduction- FIFO_RM_FULL ,
FIFO_WM_FULL

• FIFO_RM_FULL
• FIFO_RM_FULL signal is used to inform previous
  FIFO that this FIFO cant send output data in
  time. So the previous FIFO should stop feed data
  into this IP.
• FIFO_WM_FULL
• FIFO_WM_FULL signal is used to inform this FIFO
  that next FIFO cant send output data in time. So
  this FIFO should stop feed data into this IP. The
  FIFO_WM_FULL and FIFO_RM_FULL become a chain.

8
IP description
9
The IP description- required data

• IP port declaration
• IP port mapping
• IP input and output behavior
• This is the most difficult part
• INTERFACE PARAMETER
• FIFO data width

10
Example 1 AES- Port declaration

• We use Verilog type declaration
• input clkinput rstinput ldinput 1270
  keyinput 1270 text_inoutput doneoutput
  1270 text_out

11
Example 1 AES- Port mapping

• We use Verilog type mapping
• aes_cipher_top aes_cipher_top(.clk(CLK),.rst(RES
  ETN),.ld(IP_LOAD),.key(AES_KEY),.text_in(DATAOU
  T),.done(WRITE),.text_out(DATAIN))

12
Example 1 AES- input behavior

• S1 IP_LOAD lt 1b1
• S2 IP_LOAD lt 1b0
• S3 IP_LOAD lt 1b0
• S4 IP_LOAD lt 1b0
• S5 IP_LOAD lt 1b0
• S6 IP_LOAD lt 1b0
• S7 IP_LOAD lt 1b0
• S8 IP_LOAD lt 1b0
• S9 IP_LOAD lt 1b0
• S10 IP_LOAD lt 1b0
• S11 IP_LOAD lt 1b0
• S12 IP_LOAD lt 1b0

13
Example 1 AES- output behavior

• The AES use done signal to indicate that the
  output data is valid. It didnt have special
  output behavior. So leave it blank.

14
Example 1 AES- Interface parameter

• FIFO data width
• This is an important parameter. The data width
  converter will be automatic generated according
  to this parameter.
• The AES use 128-bits data width.
• FIFO_DATA_WIDTH_IN 128
• FIFO_DATA_WIDTH_OUT 128

15
Example 2 RS-DECODER- Port declaration

• input CLK
• input RESET
• input DATA_VALID_IN
• Input E_D
• input 70 DATA_IN
• output DATA_VALID_OUT
• output 70 DATA_OUT

16
Example 2 RS - DECODER- Port mapping

• RS_5_3_GF256 rs_decoder(.CLK(CLK),.RESET(RESETN)
  ,.DATA_VALID_IN(IP_LOAD),.DATA_IN(DATAOUT),.E_D
  (PIN_GND), .DATA_VALID_OUT(WRITE),.DATA_OUT(DATA
  IN))

17
Example 2 RS-DECODER- input behavior

• S1 IP_LOAD lt 1b1DATAOUT lt FIFO_DATA70
• S2 IP_LOAD lt 1b1DATAOUT lt
  FIFO_DATA158
• S3 IP_LOAD lt 1b1DATAOUT lt
  FIFO_DATA2316
• S4 IP_LOAD lt 1b1DATAOUT lt
  FIFO_DATA3124
• S5 IP_LOAD lt 1b1DATAOUT lt
  FIFO_DATA3932

18
Example 2 RS-DECODER- output behavior

• S1 IF(WRITE 1b1)FIFO_DATA lt DATAIN
• S2 IF(WRITE 1b1)FIFO_DATA lt DATAIN
• S3 IF(WRITE 1b1)FIFO_DATA lt DATAIN
• S4 IF(WRITE 1b1)FIFO_DATA lt FIFO_DATA
• S5 IF(WRITE 1b1)FIFO_DATA lt FIFO_DATA

19
Example 2 RS-DECODER- interface parameter

• FIFO_DATA_WIDTH_IN 40
• FIFO_DATA_WIDTH_OUT 8

20
Example 3 ACCUMULATOR- Port declaration

• input clk
• input nreset
• input enable
• input fifo_empty
• input 310 din
• input 40latency
• output 310 dout
• output done
• output ack

21
Example 3 ACCUMULATOR- Port declaration

• ip_accumulator ip_accumulator(
• .clk(CLK),
• .nreset(RESETN),
• .enable(ENABLE),
• .fifo_empty(FIFO_EMPTY),
• .latency(LATENCY),
• .din(DATAOUT),
• .dout(DATAIN),
• .done(WRITE),
• .ack(READ))

22
Example 3 ACCUMULATOR- input behavior

• Since accumulator use read signal, it didnt have
  special input behavior.

23
Example 3 ACCUMULATOR- output behavior

• The accumulator didnt have special output
  behavior.

24
Example 3 ACCUMULATOR- interface parameter

• FIFO_DATA_WIDTH_IN 32
• FIFO_DATA_WIDTH_OUT 32

25
IP connection description
26
Components

• BUS COMPONENT
• am_readmaster_pipeline
• am_readmaster
• am_writemaster
• IP
• ip_accumulator
• rs_decoder
• rs_encoder
• aes_cipher_top
• aes_invcipher_top

27
Connection rule

• S -gt
• Element
• Element -gt
• Element , (componentx)
• (componentx)
• Componentx -gt
• Componentx,componentx
• Component

28
Example

• S
• Element
• Element , (componentx)
• Element , (componentx) , (componentx)
• Element , (componentx) , (componentx) ,
  (componentx)
• Element , (componentx) , (componentx) ,
  (componentx) , (componentx)
• (componentx) , (componentx) , (componentx) ,
  (componentx) , (componentx)
• (am_readmaster_pipeline),(aes_cipher_top),(rs_enco
  der,rs_encoder),(am_writemaster)