AnalogtoDigital Converters in Multisystem Receivers

1
Analog-to-Digital Convertersin Multisystem
Receivers
S-87.4193 Postgraduate Course in Electronic
Circuit Design Multisystem Transceiver IC Design

• 12.12.2006
• Olli Viitala
• ovi_at_ecdl.tkk.fi

2
Outline

• Introduction
• System requirements
• Converter topologies
• Flash
• Pipeline
• ??
• Design examples
• Homework

3
Introduction

• A/D -converters needed to convert the received
  signal before demodulation in the digital domain
• In high-speed data links, from the digital
  domains PoV the ADC often forms the system
  bottleneck
• Received signal bandwidth sets the ADC topology
• In mobile multisystem terminals parallel
  converters are needed
• Reconfigurability essential to reduce complexity

4
Systems
??
Pipeline
Flash
5
System Requirements

• Type of converter needed decided by channel
• Multisystem topologies need different types of
  ADCs
• Different converters use similar sub-blocks
• Sharing reduces power, area
• Different requirements leads tooverdesign
• Circuits need adaptability
• ?? and pipeline easy to combine 1,6
• ?? can use oversampling to increase resolution

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ADC Basics

• Achievable Signal-to-Noise Ratio (for sine wave)
• SNR (6.02N 1.76) dB
• distortion is added to the real
  signalSignal-to-Noise and Distortion Ratio
  (SNDR)
• Oversampling increases SNR (digital filtering
  needed)
• SNR (6.02N 1.76 10log(OSR)) dB
• With large OSR spurious free dynamic range (SFDR)
  becomes important
• Common Figure-of-Merit

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Flash Architecture

• Conversion in one clock cycle
• Sample rates over 1 GS/s
• Resolution limited to about 6 bits
• Resolution limiting factors
• 2N-1 comparators needed
• Device mismatch
• Sample rate limiting factors
• Comparator slew-rate
• Preamplifier bandwidth

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Flash Design

• Static nonlinearities due to offsets limit
  available resolution
• averaging techniques widely used
• noise cancellation unusable due to high sample
  rate
• Bandwidth achieved using open-loop topologies
• Power dominated by preamplifiers
• interpolation efficient way to reduce power
  consumption and input capacitance
• Dynamic comparators that create charge kickback

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Pipeline Architecture

• Conversion achieved in several stages (n
  bits/stage)
• Flash sub-ADC, SH to hold the signal until DAC
  is ready
• Cascaded stages, last stage a flash ADC
• Sample rate limited to few hundreds MS/s
• Mismatch and kT/C noise keep sampling and
  feedback capacitors large
• Time-interleavingused in high samplerate
  pipelines

10
Pipeline Design

• Redundancy used in sub-blocks to compensate for
  A/D conversion errors
• 1,5 bit stage most common
• Opamp sharing techniques used to reduce power
• reset and amplifying modes non-overlapping for
  consecutive stages
• Opamp bias current can be scaled down in later
  stages
• Digital error correction schemes can be used
• Noise cancellation and gain correction

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?? Architecture

• Quantization noise is filtered only atlow
  frequencies (small BW)
• Higher order loop filter can be used
• stability problems (1st and 2nd order stable)
• Quantizer resolution can be low
• 1 bit DAC always linear
• OSR can be traded forresolution

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?? Design

• Very high resolution improvement with OSR
  increase in higher order modulators
• Loop stabilization requires multiple feedbacks
• large spread in component values
• Feedforward loop has lower spread
• only one DAC needed
• Tradeoff in loop gain between SNR and stable
  input range
• Out-of-Band interferers may cause instability

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Reconfigurability

• QoS can be implemented in the ADC
• power savings achieved with good signal
• Converted BW stays the same but resolution varies
• Pipeline can use smaller number of stages
• ?? can change OSR to change resolution 2
• Flash can use only some of comparator outputs,
  preamplifier gain can be decreased leading to
  power savings
• ADCs with OSR can decrease sampling rate
• Decimation filtering provides constant bit rate
  for DSP

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Design Example Flash 1/2

• A 5-bit 1-GS/s Flash ADC for UWB 3
• active interpolation used to reduce power
• capacitive stabilization in the reference ladder
• common-mode reset in comparators to reduce
  kickback

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Design Example Flash 2/2
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Design Example Pipeline 1/3

• A 6-10 bits reconfigurable 20 MS/s pipeline ADC
  4
• reconfigurability within 10 clock cycles
• Input stage 2/3 bit flash
• digital noise cancellation scheme reduces
  capacitor mismatch
• Gain error correction for first three stages
• 6 residue 1.5 bit stages using opamp sharing
• folded cascode opamp
• scaled bias currents

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Design Example Pipeline 2/3
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Design Example Pipeline 3/3
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Design Example ?? 1/2

• Satisfies WCDMA requirements 5
• Good performance for GSM even without
  optimization
• Second order filter with single amplifier
• Double-sampling technique
• only one sampling capacitorused in DAC
• 5-level quantization
• OSR 20

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Design Example ?? 2/2
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Design ExampleReconfigurable ADC

• 6-16 bits resolution, 0-10 MHz input BW 6
• Architecture reconfiguration ?? or pipeline
• Parameter reconf. cap. values, sub-flash
  resolution, OSR
• Bandwidth reconf. PLL changes bias with respect
  to fs

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Summary

• ADC topology decided by channel bandwidth
• no single topology for all systems (different
  topologies optimal in different operating
  environments)
• Three basic choices
• Flash high bandwidth, low resolution
• Pipeline medium bandwidth, low to high
  resolution
• ?? low bandwidth, very high resolution
• Reconfigurability added to ADCs for multisystem
  operability
• sub-block sharing (?? and pipeline)

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References

• 1 A. Baschirotto et al. Baseband Analog
  Front-End and Digital Back-End for Reconfigurable
  Multi-Standard Terminals, in IEEE Circuits and
  Systems Magazine, vol. 6, nr. 1, First Quarter
  2006.
• 2 J. Ryynänen et al. Integrated Circuits for
  Multi-Band Multi-Mode Receivers, in IEEE
  Circuits and Systems Magazine, vol. 6, nr. 2,
  Second Quarter 2006.
• 3 O. Viitala et al. A 5-bit 1-GS/s Flash-ADC
  in 0.13-?m CMOS Using Active Interpolation, in
  Proc. ESSCIRC06, pp. 412-415, 2006
• 4 W. Audoglio et al. A 6-10 bits
  Reconfigurable 20 MS/s Digitally Enhanced
  Pipelined ADC for Multi-Standard Wireless
  Terminals, in Proc. ESSCIRC06, pp. 494-499,
  2006
• 5 J. Koh et al. A 66 dB DR 1.2V 1.2 mW
  Single-Amplifier Double-Sampling 2nd-order ?? ADC
  for WCDMA in 90 nm CMOS, in Proc. ISSCC05, pp.
  170-172, 2005
• 6 K. Gulati and H-S. Lee A Low-Power
  Reconfigurable Analog-to-Digital Converter, in
  IEEE J. Solid-State Circuits, pp. 1900-1911, Dec.
  2001.

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Homework

• Find publications of ?? and pipeline ADCs (2-3 of
  each) from the 2006 Journal of Solid-State
  Circuits.
• ADCs must be intended for receivers (GSM, WLAN,
  ...)
• Collect general information of each converter
  (resolution, bandwidth, system, power,
  technology, topology, ...)
• Gather the information in a small table (max.
  size of one A4)
• The 2006 index in the December Journal could be a
  good place to start...