University%20Of%20Central%20Florida

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• University Of Central Florida
• Department Of Computer Science
• The CRAY-1 Computer System
• Presented By Hatim Boustique
• Summer 2003

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• Content
• Characteristics of Cray 1
• Computation Section
• Software
• Comparison and Evolution
• Conclusion

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Cray Seymour
Created in 1976
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• The Cray-1 consists of
• The CPU mainframe
• A power Cabinet
• A Maintenance Control Unit ( MCU)
• One or more Disk Systems
• An interface to a front-end computer

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Basic Computer System
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• Characteristics of Cray 1 Cont.
• COMPUTATION SECTION
• 12.5 nanosecond clock period
• Scalar and vector processing modes
• Twelve fully segmented functional units
• Vector ,Scalar and Address registers
• Four instruction buffers of 64 16-bit parcels
  each
• 128 Instruction codes

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• Characteristics of Cray 1Cont.
• MEMORY SECTION
• Up to 1,048,576 words of bi-polar memory (64
  data bits and eight error correction bits)
• sixteen banks of 65,536 words each
• Four-clock-period bank cycle time

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• Characteristics of Cray 1 Cont.
• INPUT/OUTPUT SECTION
• 12 input channels and 12 output channels
• Channels are grouped ( 1 group 6 channels )
• Channel groups served equally by memory
• (scanned every four clock periods)
• Channel priority resolved within channel groups
• Lost data detection

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• Computation Section

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• Computation Section consists of
• Instruction Control Network
• Operating registers
• Functional Units ( Or pipelined Units)
• Instruction buffers

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Computation Section ( cont.)Instruction format
Example Arithmetic operations gh operation
code i the result register j and k the two
operand registers
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Computation Section ( cont.)Operating registers

• V Registers for Vector processing
• 8 V registers
• ( 1 V Register 64 elemt)
• ( 1 Element 64 bits)
• Suited for vector quantities ( i.e. rows/columns
  of matrices)
• Used for vector chaining

M E M O R Y
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Computation Section ( cont.)Operating registers

• Example of Chaining
• DO I 1, 64
• D(I) A(I) B(I) C(I)

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Computation Section ( cont.)Operating registers

• - S Registers for Scalar processing
• 8 S-registers
• ( 1 Register 64 bits)
• Source and destination for scalar arithmetic
• Furnish one operand in vector instructions

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Computation Section ( cont.)Operating registers

• A Registers ( Address )
• 8 24-bit registers
• Primarily for
• - Memory references
• Also for
• Loop control
• Channel I/O operations

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Computation Section ( Cont. ) Functional Units

• Hardware organizations
• Each implements a portion of the Instruction Set
• 12 independent functional units parallelism
• grouped into
• Vector units
• Floating point
• Scalar units
• Address units

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Computation Section ( Cont.) Functional Units
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Computation Section ( Cont. ) Functional Units
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• Software
• Cray Operating System (COS) up to
• 63 jobs in a multiprog. Environment
• Cray Fortran Compiler (CFC)
• optimizes Fortran IV (1966) for the Cray-1
• Automatically vectorizes loops that
• manipulate arrays

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Front-end computer Any computer, such as a Data
General Eclipse or IBM 370/168

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Comparison with HP9000/735
HP9000/735 workstation 1992 Cray-1 Vector Supercomputer 1976
gt130 MIPS lt 10 MIPS
41 MFLOPS 27 MFLOPS
Price 40,000 4,000,000
99 MHz 80 MHz
Cache 128 kB 0.25 kB
Mem 400 MB 32 MB
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Evolution Of Cray
CRAY-1 CRAY-2 CRAY-3 CRAY-4
1976 1984 1988-89 1992
CP 12.5ns CP 4.1ns CP 2ns CP 1ns
1 CPU 4 CPUs 16 CPUs 64 CPUs
80 MIPS 480 MIPS 8000 MIPS Cray Computer Corporation declared bankruptcy
160 MFLOPS 1800 MFLOPS 16000 MFLOPS Cray Computer Corporation declared bankruptcy
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Conclusion

• To which category of architectures The Cray 1
  Computer does belong ?
• Load Store
• Parallel functional units
• Pipeline processing

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References

• - Russell, R. M., "The CRAY-1 Computer System",
  Communications of the ACM, (21) 1, January 1978,
  pp. 63-72
• - Cray-1 Computer System
• Hardware Reference Manual 2240004By CRAY
  RESEARCH, INC. 1976.