CMS Tracker Readout Effort Requirements in Instrumentation Department

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CMS Tracker ReadoutEffort Requirements
inInstrumentation Department

• John Coughlan

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CMS Tracker Readout Summary

• Overview.
• Scope of project in INS
• Team members
• Project Status
• List of tasks to completion
• Effort required
• Summary Comments

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CMS Tracker ReadoutOverview
Task To readout a very large Silicon Tracking
detector. 9 million Silicon Strip channels ON
Detector 73K APV25 pipeline chips _at_ L1 Trigger
MUX APV Frame output Analogue Data readout via
Optical links (APV Frame Header Strip Data) gt
INS Effort essentially complete OFF Detector
Front-End Drivers (FED) Digitise / Zero Suppress
/ DAQ readout 500 x 9U VME64x boards (incl
spares) 96 ADC channel boards gt INS Effort
major activity
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Hybrid
Front-End Hybrid
Silicon Strips
70m
On Detector (Hard Radiation)
FPGA
DAQ
Counting Room
VME 9U FEDs
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CMS Tracker FED Block Diagram
96 Tracker Opto Fibres
CERN Opto- Rx
Modularity 9U VME64x Form Factor Modularity
matches Opto Links Data suppression board. 8 x
Front-End modules OptoRx/Digitisation/Cluster
Finding Back-End module / Event Builder VME
module / Configuration Power module Other
Interfaces TTC Clk / L1 / BX DAQ Fast
Readout Link TCS Busy Throttle VME Control
Monitoring JTAG Test Configuration
9U VME64x
Analogue/Digital
JTAG
FPGA Configuration
FE-FPGA Cluster Finder
VME Interface
VME-FPGA
BE-FPGA Event Builder
TCS
TTC
TTCrx
DAQ Interface
Buffers
Power DC-DC
Temp Monitor
Front-End Modules x 8 Double-sided board
Xilinx Virtex-II FPGA
TCS Trigger Control System
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CMS Tracker FED Data Processing
96 Tracker Opto Fibres
CERN Opto- Rx
9U VME64x
Data Suppression 9U VME64x Form Factor Analogue
96 ADC channels (10-bit _at_ 40 MHz ) _at_ L1 Trigger
processes 25K MUXed silicon strips / FED Raw
Input 3 Gbytes/sec after Zero
Suppression... DAQ Output 200 MBytes/sec (_at_
L1 max rate 100 kHz) Digital
Processing Flexible Digital Logic Xilinx
Virtex-II FPGAs 40K-gt3M gatesFPGAs programmed in
VHDL VERILOG
Analogue/Digital
JTAG
FPGA Configuration
FE-FPGA Cluster Finder
VME Interface
VME-FPGA
BE-FPGA Event Builder
TCS
TTC
TTCrx
DAQ Interface
Buffers
Power DC-DC
Temp Monitor
Front-End Modules x 8 Double-sided board
Xilinx Virtex-II FPGA
TCS Trigger Control System
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CMS Tracker FED Board Layout Primary Side

• Complex board
• Pushing density limits on large board for cost
• Opto Analogue Digital issues
• Brings together considerable INS Dept expertise
  and experience from several areas into one project

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CMS Tracker FED Board Layout Primary Side
Double sided
View thru the board
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FEDv1 Front-End module Primary Routed
OptoRx
ADCs
OpAmps
40K FPGAs
1500K FPGA
Note FPGA de-coupling
Dense circuitry
12 optical channels
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CMS Tracker FED Transition card option
Due to mechanical constraints place DAQ link card
on Transition card
Transition Card
Very simple card
BE-FPGA Event Builder
DAQ Mezzanine Card
TTC
TTCrx
DAQ Front-end Readout Link FRL
S-LINK64
Buffers
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CMS Tracker FED INS Main Deliverables (Project
Spec)

• RAL INS
• RAL PPD
• Imperial College
• Brunel

FED project institutes

• Includes
• Design of 9U FEDs. Electrical tests of design.
• Design Testing Baseline FPGA Firmware.
• Production of prototypes for CMS silicon tests.
• Production and Testing of 500 FEDs (incl
  spares.)
• Transition cards for DAQ links (optional)
• Low level driver software.
• Full Documentation.
• Communication with CMS groups
• Assistance during Tracker installation
  commissioning.

• Excludes
• OptoRx design testing.
• Opto Test equipment for FEDs.
• DAQ link mezzanine card.
• High level software.
• Provision of VME crates and cabling.
• Other modules in FED VME crates e.g. CPUs.

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CMS Tracker FED Team Members in INS
Moving from Design phase to Test phase...

• Core Team
• John Coughlan
• Project Manager CMS Link
• Software
• Saeed Taghavirad
• Hardware Design Firmware
• Ivan Church
• Test Engineer

• Plus
• Ed Freeman
• Firmware
• James Salisbury
• Analogue Design
• Rob Halsall
• Technical Advisor
• Others
• Design Office
• Procurement
• Additional Test support

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CMS Tracker FED Project Status

• 1998-gt2001
• FED-PMCs x 60 produced for CMS Silicon module
  testing.
• Small nr channels with limited functionality.
• Cheap. Very flexible. Plug in PC or use in VME
  crate.
• Very popular with CMS! (and others)
• 2001
• Final 9U FED design started in earnest.
• Requirements document produced.
• Algorithms studied. Board interfaces
  investigated.
• Choice of (NEW) FPGA family made. (Cost critical)
• 2002
• Implementation of design 96 chan ADC on 9U.
• Analogue design complete (OptoRx finalised by
  CERN).
• Cluster finding algorithms implemented in
  Firmware.
• DAQ interface baseline decided.
• Basic simulations and test bench measurments
  made.
• Components chosen. Board layout Routing.
• Manufacture of first pair of FEDv1s.

FED-PMC (FED prototype)
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CMS Tracker FED INS Dept Outline Tasks

• 2002
• Manufacture 2 x FEDv1.
• 2003
• Test FEDv1 design
• Analogue electrical tests (Opto tests _at_ IC)
• Firmware (Cluster finding Event readout)
• VME Interface
• DAQ interfaces (with IC)
• Driver software
• Production and Testing of 20 FEDv1s for CMS
  tracker testing.

• 2004
• Pre-Production and Test of 20 x FEDv2.
• Start procurement for 500 FEDs.
• Set up for production Tests.
• 2005 (tasks in parallel)
• Manufacture of 500 FEDv3.
• Production Testing _at_ RAL.
• Assist Installation Commissioning _at_ CMS.
• 2006
• Complete commissioning _at_ CMS.

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CMS Tracker FED INS Dept Effort
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CMS Tracker FED Comments

• Effort projections (made in 2000) have not been
  adjusted.
• Allocations should be sufficient given following
  assumptions
• Effort profile needs adjusting to reflect
  schedule changes (carry over this year).
• Assumes no major re-design of FEDv1 to FEDv3 for
  production.
• Assumes no further schedule slippage
  (installation in 2005)
• No contingency needed (e.g. for staff turnover).
• Assumes personnel with key skills (eg. FPGA
  design) stay with project.
• Assumes assistance in automated FED production
  testing.
• Assumes little or no support for FEDs with CMS
  tracker module testing.
• But Installation commissioning effort will not
  be sufficient.

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FED Design Testing
96 Tracker Opto Fibres
CERN Opto- Rx
Detailed Design Test Plan JTAG Boundary Scan
Digital connections Chip Scope Integrated Logic
Analyser Cores Capture raw ADC data (without
VME) Opto-Tests or Inject electrical signals
post-OptoRx Special FPGA loads e.g. Pattern
Generators Additional Test Features Internal/Ex
ternal Clocks External Triggers
9U VME64x
Analogue/Digital
JTAG
FPGA Configuration
FE-FPGA Cluster Finder
VME Interface
VME-FPGA
BE-FPGA Event Builder
TCS
TTC
TTCrx
DAQ Interface
Buffers
Power DC-DC
Temp Monitor
Front-End Modules x 8 Double-sided board
Xilinx Virtex-II FPGA
TCS Trigger Control System
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CMS Silicon Strip Tracker FED Status
96 Tracker Opto Fibres
CERN Opto- Rx
9U VME64x
Analogue/Digital
JTAG
Board Status
FPGA Configuration
FE-FPGA Cluster Finder
VME Interface
VME-FPGA
BE-FPGA Event Builder
TCS
TTC
TTCrx
DAQ Interface
Buffers
Power DC-DC
Temp Monitor
Front-End Modules x 8 Double-sided board
Xilinx Virtex-II FPGA
TCS Trigger Control System
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CMS Silicon Strip Tracker FED Summary Schedule
FF1 Full scale Prototype FF2
Pre-production FF3 Final production
Summary Presented a 9U VME64x board for
off-detector readout of Silicon Strip
Tracker Digitisation Zero Suppression Event
Readout Meets SST data rate requirements Analogue
96 channel 10-bit ADC _at_ 40 MHz Digital
Virtex-II FPGAs flexible logic Test and Monitor
features aid debugging
Schedule 2002/Q4 2 x FF1 _at_ RAL for
test 2003/Q4 10 x FF1 _at_ CERN 2004/Q4 10 x
FF2 manufacture 2005/Q2 500 x FF3
manufacture (funds permitting)
http//www.te.rl.ac.uk/esdg/cms-fed/index.html
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CMS Silicon Strip Tracker FED Summary Schedule

• In order to achieve minimum firmware software
  on TIB timescales require...
• Confirmation of functionality needed for TIB
  tests.
• Close co-operation between UK and Tracker DAQ
  group.
• Arrange small FEDv1 online meeting.
• Propose contact from UK to visit CERN for
  technology transfer.
• Keep systems h/w and s/w as close as possible
  (within UK) and between UK and CERN.
• Note We now have additional effort in UK for
  test software, database, etc.
• See Testing Talk

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CMS Silicon Strip Tracker FED Counting Room
Layout (illustration)
FED
DAQ

• 40 K ADC Channels 10 Bit_at_40MHz
• Max Trigger Rate 100 kHz
• Input Rate 1.5 T Byte/s
• Output rate 25 Gbyte/s/

• 440 Boards 96 ADC/Board
• 24 Crates
• 8 Racks

4 TTC Partitions
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FED Schedule
FEDv1 Full scale Prototype FEDv2
Pre-production FEDv3 Final production
Schedule 2002/Q4 2 x FEDv1 _at_ for UK test Batch
1 2003/Q4 10? x FEDv1 _at_ CERN Batch
2 2004/Q4 10? x FEDv2 manufacture 2005/Q2
500 x FEDv3 manufacture (funds permitting)
OptoRx added post-assembly. Procurement
started for critical parts for Batch 2
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FED TIB Test Schedule
Q. Deliver 2 x FEDv1 Batch 1.5 _at_ CERN for TIB
test starting July 2003 ??

• Very tough. Testing is a big job. Cant promise
  to deliver in June?
• Use Batch1 PCBs. ie No design iteration possible.
• Risk that design has major fault.
• Prioritise essential firmware and testing plan.
• Require explicit list of functionality essential
  for the TIB assembly centre.

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FED TIB Test Schedule