Towards the Electronics for the ACTIVE TARGET

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Towards the Electronics for the ACTIVE TARGET

• P. Baron, D. Calvet, E. Delagnes,
• F. Druillole, E. P.
• CEA SACLAY
• FRANCE

Emanuel Pollacco DAPNIA/SPhN, CEA Saclay
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ACTAR Project

• A four year EU Program
• Physics
• Rates/ dynamic ranges/ triggers/
• Geometry/Magnets topology
• Gases to be employed
• Gas amplification (Wire/µOmegas/GEM)
• Electronics Systems
• Analysis
• Electronics System highly dependent on
• ?1 to 4 5 ? need versatile set-up

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NuStar
Si/CsI
SPIRAL2 ALPI
QP
DE.E
DI
PSD
Active Target
TOF
Si based threshold

Bolormeters
Emanuel POLLACCO CEA Saclay
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(No Transcript)
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DSM
Astrophysics, High Energy Physics, Nuclear
Physics and associated instrumentations
Division J. Zinn Justin (600)
DAPNIA
SIS
SACM
SEDI
SPP
SPhN
SAp
(Detectors, Computing, Electronics Department) M.
Mur (150)
LSEO
TRAPS
LDEF
LID
LIS
Detector RD and Front-End Electronics Lab E.
Delagnes (23, 6 chip designers)
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The LDEF Expertise Skill boundaries.

• Study and conception of analog or mixed analog
  digital ASICs
• Full custom for analog circuits.
• Full custom or standards cells for digital
  circuits.
• Prototypes Test. Production Test bench
  Development.
• Manual writing (French English)
• Main Fields Of interest
• Low Noise, Low Power Front-ends for capacitive
  Detectors.
• Analog Memories (Very High Speed and High dynamic
  range).
• Large dynamic range front end for nuclear
  physics.
• MAPS for High Energy Physics

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Evolutions ASIC map
E. Delagnes_at_cea.fr
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• AFTER ELECTRONICS for
• the T2K TPC

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The T2K experiment
Time schedule Q3 2009

• Goal Study of neutrino oscillation
• J-PARC 50GeV synchrotron (under construction)
• ND280m Near detector at 280m from the neutrino
  production target

J-PARC,Tokai
Super Kamiokande
ND280
Kamioka
Magnet Field 0.2T
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AFTER A design adapted to the T2K-TPC initial
requirements and constraints

• Store and digitize the detector signal.
• Must be versatile to be usable with various
  end-plate detectors and gas
• compatible with both polarities of signal,
  programmable gain
• Sampling frequency adjustable
• Low cost.
• Short time development (2 years for the all
  electronics)
• gt architecture-limited risks use of mature
  technologies.
• Minimum power consumption (detector inside
  magnet).
• Minimize the cabling between detectors and
  acquisition
• Can function in a magnetic field.
• Limited dynamic range for Active Target
• Max DAQ rate 20Hz need 1KHz
• No internal trigger available-needed for Active
  Target

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Layout Package

• Power consumption 5-7 mW/ch 0.5W total

• Technology AMS CMOS 0.35µm
• Area 7.8 x 7.4 mm2
• Package LQFP 160 (28x28x1.4 mm)
• Prototype Run April 2006
• Delivery August 2006
• Production End 2007 3000 chips

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A highly multiplexed architecture to reduce the
power consumption taking benefit of the low event
rate

• FE Architecture similar to those of the LBL
  electronics for the STAR TPC, but more compact
  and taking benefit of new technologies.
• AFTER chip including 72-channel of FE and SCA and
  multiplexer.
• Minimize the number of high speed ADCs (disabled
  when not converting).

72x4(8)x12 3.5k (7k)
Signal amplified stored in a SCA until
external stop, then muli No zero supress. No
auto triggering.
At stop, digitization of all the channels. 2ms
for the total data of the SCA
On-detector Data concentration. Zero
supression. Data compression
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Some idea of the data Transfer

• AFTER (72 4) channels x 512 cells 140 for
  ACTAR
• At 50MHz ? 3x1014
• AFTER one event ? 76x51277.8kbyte (12bit16bit!)
• FEC 4 (AFTER ADC20MHz)
• 288 channels 35 for ACTAR
• At 50MHz Trigger ? 300 kbytes 1.9 msec ie
  theoretical Max. 500 Hz
• FEM 4(FEC)
• 1152 channels 9 FEM for ACTAR
• At 50MHz Trigger ? 1.2 MByte
• Remove zeroes ? say 1/10 ? 120kbyte (Assume)
• DCC 12(FEM) 1 for DCC for ACTAR
• At 50MHz Trigger ? 1.44 MByte (No zero removal
  14Mbyte?224Mbit)
• At 100events/sec ? 144Mbyte ? 2.3Gbit/sec

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AFTER Main Features

• No zero suppress.
• No auto triggering.
• No selective readout.

• Main features
• Input Current Polarity positive or negative
• 72 Analog Channels
• 4 Gains 120fC, 240fC, 360fC 600fC
• 16 Peaking Time values (100ns to 2µs)
• 511 analog memory cells / Channel
• Fwrite 1MHz-50MHz Fread 20MHz

• Slow Control
• Power on reset
• Test mode
• calibration or test channel/channel
• functional 72 channels in one step
• Spy mode on channel N 1
• CSA, CR or filter out

P. Baron_at_cea.fr
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A question of gains

• Consider 600fC in 12 bits
• Noise 1000e?0.16fC?Ch 1 Noise
• 2keV/cm with Gain 100 ? 1.4fC? Ch 10 for Pions
• 850keV/cm with Gain 100?595fC?Ch 4060 for Li
• Need to increase the dynamic range?
• More bits slower ADC frequency is it possible?
• At the shaper level?
• At the PA input stage? - how
• Logarithmic, semi logarithmic pre-amp?
• ?Needs a study.

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Architecture FE
P. Baron_at_cea.fr

• CSA
• NMOS 2000µm/0.35µm
• Cf Cf200fF, 400fF, 600fF 1pF
• Rf Attenuating Current Conveyor
• 4 values Rf.Cf100µs
• Polarity positive or negative
• Pad (Vdc 2V)
• NMOS input current tunable

• Gain - 2
• Output Dynamic
• 1.5V (full range)
• Buffering for SCA
• Polarity Vdc pad
• (anode polarity0.7V)
• For Vicm Vocm

• PZC
• Zero CpRp CfRf
• Rp Attenuating Current
• Conveyor of CSA
• Pole RsCs 16 values
• (50ns to 1µs)
• Polarity Vdc pad
• (anode polarity2.2V)

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Pulse Shape
FWHM
P. Baron_at_cea.fr
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Pulse Shape linearity
Peaking Time 100ns
Measured INL lt 1.2 Full range
Perfectly working for a 100MHz wck
Pulse shape independent of amplitude
P. Baron_at_cea.fr
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AFTER measured Equivalent Charge
ENC ENC0 (tp, ICSA) a (tp, ICSA). Cin
dot measured line quadratic parametrization
P. Baron_at_cea.fr
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AFTER ENC on FEC
22pF added
no added capacitor
difference between the 2 other meas.
noise uniformity on a chip (100ns peaking time.
120fC range). .
noise uniformity on detector .
P. Baron_at_cea.fr
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Crosstalk

• On chip xtalk lt /- 0.4 (prop to distance)
• But because of ac coupling with detector and
  parasitics between pad
• 1.2 non derivative Xtalk
• to 2 neighbourghing pads.

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p-Pb interactions
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AFTER Micromegas

• 8.5 rms resolution on 55Fe peak

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Detector Module Read-out Electronics (1728 ch)
288-channel analog Front-End Card (FEC)
1728-pad detector plane
80-pin connector
72-channel ASIC
Slow-control Network - CANbus
Quad-channel ADC
digital Front-end Mezzanine card (FEM)
FPGA
Fiber to DCC
Optical Transceiver
Low voltage power

• Materializing the concept
• Concept first shown March 05 (4 FECs/FEM)
  Prototype in Sept. 07
• ? Important milestone reached exploitation in
  progress

D. Calvet_at_cea.fr
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TPC Plane Readout
Off-detector
Inside the Magnet
TPC plane
12 optical fibers
Detector Module
Front- End Card
Front-End Mezzanine card
Optical link
Data Concentrator Card
x 6

• 1 of 6 TPC planes shown 3 TPC stations
• 6 x 2 detector modules per TPC plane 72 modules
  in total
• 1 duplex optical readout fiber per detector
  module
• 1 external data concentrator per TPC plane 6
  concentrators in total

D. Calvet_at_cea.fr
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Off-Detector Concentrator Card
Optical transceivers
Main data
VME or PCI
Slow control
Main data 1-2 Gbit/s
Slow control data
FPGA logic
Slow control commands
Global clock
Trigger
Global clock
Trigger

• Principles
• Standard form factor (6U or 9U) VME or Compact
  PCI backplane bus
• Clock, trigger and control signals fanout, slow
  control interface

D. Calvet_at_cea.fr
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TPC Event Building, DAQ Interface
6 concentrators
Detector A
VME/PCI backplane bus
Common DAQ Run Control
Network
TCP/IP
Gigabit Ethernet
Commercial Linux PC
Detector B
Global Clock Trigger
Detector TPCs

• Principles
• Event Building for TPC data over backplane bus
  with a PC or each concentrator send data directly
  to the DAQ via a Local Area Network connection
• Interface to common DAQ system via standard
  Gigabit Ethernet LAN
• TPCs (like other detectors) compliant to the
  experiment wide physical interface
  specifications, protocols and software framework

D. Calvet_at_cea.fr
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New version of AFTER under discussion

• Mainly for Nuclear Physics needs
• As compatible as possible with AFTER.
• Same technology.
• Possible changes/additions under discussion
• Self triggering capabilities - On-chip zero
  suppress
• LED (8bits over 10 of dyn.range)/channel
• Analogic Sum of LED ? Trigger out
• Disc. Register ? Selective-readout (from Idef-X
  chip)
• Disc. Register ? Calculated Selective-readout?
• Shaping time 50ns. To cover 50nsec to 2µsec
• True integrating mode available ( frequency
  pole of PZC stage increased)
• Introduction of external pre-amplifier
• ADC (12 bit 20MHz) Presently card FEC one
  ADC/AFTER
• Consider 2 ADC/AFTER ? equivalent 40MHz
• ?? 7 months micro-engineering time
  submission
• Goal Specifications frozen in Jan 2008

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New version of AFTER under discussion
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New version of system under discussion

• External Pre-amp
• Consider independent slow control gain setting
• Mechanics definition, cable definition etc
• ASIC setting (AFTER)
• ?? 6 months µ-electronic engineer
• FEC
• 6 (AFTER ADC memory)
• FEC
• 4 (AFTER 2ADC 2memory)
• Require
• Mechanics definition
• 6 man-month engineer for the electronic hardware
• FEM
• FPGA ? Vertex2 ? FEM ? Vertex4/5
• Definition of requirements
• Continuous data flow option
• Data reduction to be placed on FEM
• 4 FEC/FEM More computing speed
• gt12 man-month engineer for the firmware

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END