ECE 291: Senior Design Team

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ECE 291 Senior Design Team 1

• Reed Solomon Decoder for HDTV Applications

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Team Members

• Enrique Aleman
• Emmanuel Galema
• Mathew Kettledon
• Advisor Hanho Lee
• Sponsor ECE Department

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Overview

• What is Reed-Solomon code?
• Theory behind the code
• How this works for High-Definition TV
• C code (For verification)
• Verilog HDL Coding
• Synthesis for a FPGA (Field Programmable Gate
  Array).

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Reed-Solomon Code

• Block based error correction code
• Used in a wide variety of applications.
• Ex CD, DVD, Satellite communications, HDTV, and
  communication networks.
• Parity bits redundancy
• Can correct entire bytes of error

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Reed-Solomon Code

• RS(n,k)
• n codeword symbols
• k data symbols
• n k parity symbols 2t
• t maximum of symbol errors that can be
  corrected.
• S number of bits per symbol ?index

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Representing Alpha(?) values
P(x) X8 X4 X3 X2 1 for GF(28) P(?)
?8 ? 4 ? 3 ? 2 1 0 Ex. ?9 /
P(?) ?1 ?3 ?4 ?5
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Galois Field Algebra

• Field a number system with defined fundamental
  operations (, -, /, x)
• Galois Field (GF) is a finite field
• GF(2m ) ? m8
• Multiplication ? i ? j ?(i
  j) mod (2m - 1)
• Division ? i / ? j
  ?(i - j) mod (2m - 1)
• Example ? 5 ? 4 ? 9 mod 7 ? 2
• Addition/Subtraction ( use binary XOR)
• Example ? 17 ? 18 (00011001) (10110100)
  (10101101) ? 42

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HDTV

• What is HDTV?
• New television standard
• Prone to errors
• Uses a Reed-Solomon Decoder to reduce Bit Error
  Ratio (BER) in HDTV.

• HDTV uses RS(207,187)
• S ?index byte 8 bits
• t 10 symbols 80bits

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Reed-Solomon Encoder

• Generator Polynomial
• Encoder Algorithm
• c(x) xn - k m(x) mod g(x)

• g(x) (x?)(x?2)(x?19)(x?20)
• c(x) encoded message
• m(x) original message polynomial
• xn - k m(x)/g(x) q(x) c(x)/g(x)

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Reed-Solomon Decoder

• RS decoder consists of
• Syndrome calculator
• Euclidean algorithm block
• Chien searcher
• Forney algorithm block
• Error corrector
• FIFO

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Syndrome
Where r(x) e(x) c(x)

• Syndrome
• S(x) r(x) mod g(x)
• Depends only on e(x)
• r(x)/g(x) q(x) S(x)/g(x)
• e(x) c(x)/g(x) q(x) S(x)/g(x)
• Since c(x) is divisible by g(x)
• e(x)/g(x) qe(x) S(x)/g(x)
• Consists n-k symbols used to limit the search
  for the e(x) from 2n to 2n-k.
• If there are no errors, the syndrome polynomial
  S(x) will be zero.

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Euclidean Algorithm

• Euclidean algorithm
• Processes the key equation, S(x)?(x) ?(x) mod
  xn k to generate an error locator polynomial
  ?(x) and an error magnitude polynomial ?(x).
• Determines the greatest common divisor of the two
  polynomials.

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Euclidean Divider Block
?Q1(x)
?Q2(x)
Initial Values
R -1(x) x 20
R0(x) S(x) ? x 19 x18 1
?R2(x)
Since deg R2(x) lt ( T 10) ?(x) R2(x)
?R1(x)
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Euclidean Multiply Block
.
.
B1(x) B -1(x) Q1(x) B0(x)
Initial Values
B -1(x) 0
B2(x) B 0(x) Q2(x) B1(x)
B0(x) 1
B3(x) B 1(x) Q3(x) B2(x) B1(x)
B4(x) B 2(x) Q4(x) B3(x) B2(x)
?(x) BT(x) B !0(x) B 2(x)
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Chien Search Block

• Chien Search
• Evaluates the error locator polynomial ?(x) to
  find its roots. It runs all possible input
  values of the GF(256) and then checks to see if
  the output is zero. A value of zero at the
  output indicates an error at that location.

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Forney Algorithm and Error Corrector Block

• Forney Algorithm
• Computes the error magnitudes ( Yi ) with the use
  of ?(xi) and ?(xi).
• Yi ?(xi) / ?(xi)
• Where xi indicates the root as computed from the
  Chien Search and ?(xi) is the derivative of
  ?(x).
• Output of this stage is the completed error value
  e(x).

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Forney Algorithm and Error Corrector Block.

• Error Corrector
• Takes the received word r(x) and adds
  (XOR-operation) it to the corresponding error
  magnitudes computed at the respective error
  locations to produce the corrected codeword.
• r(x) e(x) c(x)

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Design Flow
 

• Define requirements specify functionality of
  device. Ex I/O and performance requirements

Define Requirements

• C coding Source code of a program that
  implements a Reed-Solomon encoder/decoder.

C coding
Verify Logic

• Verilog coding entry functional description of
  architectures. Include combinational logic design
  and RTL (Register Transfer Level) coding.

Verilog Coding
Verify Logic
Synthesis

• Synthesis generates a netlist from the Verilog
  code. Netlist is a low level abstraction of the
  code.

Verify Logic
Place Route

• Place and Route determines the Placement of each
  cell and connections between cells in the chip.

Verify Logic
Configuration

• Configuration a process in which the circuit
  design (bitstream file) is downloaded into the
  FPGA.

FPGA Chip
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C Code Implementation

• Source code of a program that implements the
  Reed-Solomon decoder/encoder algorithm
• Verification purposes

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Outputs of C Code
RS(7,3)
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Verilog HDL code

• Simple example of Verlilog
• module mux2x1 (A, B, Sel, Y) input 7 0
  A input 7 0 B input Sel output 7
  0 Y reg 7 0 Y always _at_ (A or
  B or Sel) Y lt (Sel) ? B A
  endmodule // mux2x1

Gate Level Diagram of MUX2x1
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Verlilog Simulation Result
RS(207, 187) C code comparison Index
Errmag_out Received corrected
Original6, 0,
212, 212
2127, 0,
244, 244
2448, 0, 4,
4 49,
12, 205, 193
19310, 232,
64, 168
16811, 186,
8, 178
17812, 0,
216, 216 21613,
39, 2,
37 3714,
0, 76, 76
7615, 158,
29, 131
13116, 0,
47, 47
4717, 0, 250,
250 25018,
204, 16,
220 220
?End
?Begin
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Implementation

• FPGA design for RS decoder

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Synthesis for FPGA

• Macro Statistics
• Registers 22
• 8-bit register 22
• Multiplexers 22
• 2-to-1 multiplexer 22
• Xors 188
• 1-bit xor10 1
• 8-bit xor10 1
• 1-bit xor2 118
• 1-bit xor3 55
• 1-bit xor4 2
• 1-bit xor5 2
• 8-bit xor5 1
• 1-bit xor6 2
• 1-bit xor7 3
• 8-bit xor7 1
• 1-bit xor8 1
• 1-bit xor9 1

Example HDL Synthesis Report for the Chien
Search block.
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Timeline
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Budget

• Verilog Simulator
• FPGA Chip
• CAD Tool
• Chip Board
• Hardware for testing
• Time Spent

• 0
• 0
• 0
• 0
• 0

• PRICELESS

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QUESTIONS

• ?