Test Data Generation for LRU CacheMemory Testing

1
Test Data Generation for LRU Cache-Memory Testing

• Evgeny KornikhinMoscow State UniversityInstitute
  for System Programming of RAS

2
testing by test programs
add r1,r2,r3sub r4, r1, r2lw r5, r1, 0lui r2,
r1, r4
Y/N
assembly program ( test program )
microprocessor
3
test program generation
model of microprocessor
coverage oftest situations and dependencies
(r-w, r-r)
add r1,r2,r3 _at_ overflow lw r4, r3, c _at_ hit
test templates
(logical form)
mov r2, 0xFF add r1,r2,r3 lw r4, r3, 0
test programs
(executable form)
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test program generation
model of microprocessor
coverage oftest situations and dependencies
(r-w, r-r)
add r1,r2,r3 _at_ overflow lw r4, r3, c _at_ hit
test templates
(logical form)
mov r2, 0xFF add r1,r2,r3 lw r4, r3, 0
test programs
(executable form)
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test program generation
model of microprocessor
coverage oftest situations and dependencies
(r-w, r-r)
add r1,r2,r3 _at_ overflow lw r4, r3, c _at_ hit
test templates
(logical form)
mov r2, 0xFF add r1,r2,r3 lw r4, r3, 0
test programs
add specific initialization of microprocessor
(registers and cache)
(executable form)
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cache-hit
cache model
tag0'
value0'
tag0''
value0''
set ?0
LOAD val, addr (val memoryaddr)
t'
v'
t''
v''
set ?s
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cache-hit
cache model
tag0'
value0'
tag0''
value0''
set ?0
LOAD val, addr (val memoryaddr)
addr
t t' ort t''
s
t
t t''
tag
set
t'
v'
t''
v''
set ?s
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cache-miss
cache model
tag0'
value0'
tag0''
value0''
set ?0
LOAD val, addr (val memoryaddr)
addr
nextlevel
t ! t' andt ! t''
s
t
tag
set
t'
v'
t''
v''
set ?s
evicted
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problem again

• LOAD x, y _at_ hitSTORE u, z _at_ missLOAD z, y _at_ hit

initial state of cacheand registers ?
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key idea
test template
add ...load sub div
LOAD x, y _at_ hit
constraint
variable
?
?
?
?
y ? a,b,c
?
?
variable
u ? a,b,c
cache model
x z
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fully associative cache
z
x
x
y
z
...
N
y
x,y,z,... - current state
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cache-hit hit(t)
z
t
x
x
y
z
...
N
y
t ?x,y,z...
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cache-miss miss(t)
z
t
x
x
y
z
...
N
y
t ? x,y,z...
new cachex,y,z...?t\?
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cache-miss miss(t)?u
z
t
x
x
y
z
...
N
y
t ? x,y,z...
u?x,y,z...
new cachex,y,z...?t\u
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lru(u)
hit x1
u x2
hit x2
x3, x5 L\u
miss x3-gtx4
hit x5
L
miss t-gtu
counter(u)min
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lru(u)
hit x1
u x1
hit x2
x2, x3, x5 L\u
miss x3-gtx4
hit x5
L
miss t-gtu
there are another cases
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example
a
initialstate
b
y?a,b,g
g
z?a,b,g
LOAD x, y _at_ hit
z0?a,b,g
?z0
STORE u, z _at_ miss
z0b a,b,g\z0g,y
LOAD z, y _at_ hit
y?a,b,g,z\z0
N 3
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example
z?a,b,g
y a
y?a,b,g
z?a,b,g
ya0
z0?a,b,g
z0b a,b,g\z0g,y
b1
g2
z3
y?a,b,g,z\z0
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common cache
x
x
R(x)
y
R(y)
y
z
z
R(z)
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common cache
hit(t)
t ? L
miss(t)?u
u ? Lt ? L new cacheL?t\uR(t) R(u)lru(u)
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lru(u)
hit x1
hit x2
u x2
x3, x5nR(u) (L\u)nR(u)
miss x3?x4
hit x5
miss t?u
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example
x1,x2 ? a1,a2,b1,b2,c1,c2
x3 ? a1,a2,b1,b2,c1,c2
R(x3) R(y3)
x4 ? a1,...,c2,x3\y3
x5 ? a1,...,c2,x3\y3
y3 c2
y3 (a1,...,c2\x1,x2, y3)nR(y3)
y5 x2
y5 (a1...c2,x3\y3,y5, x3,x4)nR(y5)
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solver
(assert (or ( x a) ( x b)( x c)))
x ? a,b,c
y ? a,b,c
(assert (and (/ y a) (/ y b)(/ y c)))
x z
(check)
SMT

• SAT modulo theories (bit-vectors)
• Yices

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contacts

• http//tesla-project.googlecode.com
• http//hardware.ispras.ru
• kornevgen_at_gmail.com