Architecture-Level Power Modeling

1
Architecture-LevelPower Modeling

• N. Kim, T. Austin, T. Mudge, and D. Grunwald.
  Challenges for Architectural Level Power
  Modeling. In Power Aware Computing, (R. Melhem
  and R. Graybill eds.), Kluwer, 2001.
• Kevin Skadron
• Mircea Stan

2
Who Cares?

• Power is now a first-level design constraint for
  both embedded/mobile and high-performance/general-
  purpose processors
• Battery life (eg, laptops)
• Heat removal and package cost
• Degradation and lifetime
• Architects dont have good tools to model this

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Modeling

• What architects normally do model
  behavior/performance at the cycle level (eg,
  SimpleScalar)
• Many abstractions and simplifications
• Examples I-cache, memory buses
• Faster than a more detailed model still good
  enough
• Power and heat, however, require more
  implementation detail
• Current power-performance simulators try to omit
  the extra detail by using abstractions or
  analytic models

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Current Arch.-Level Power Simulators

• Wattch (Brooks et al.)
• Doesnt model anything outside the core (eg,
  external bus)
• CACTI-based models for large structures (cache,
  branch predictor, register file, instruction
  window, etc.)
• Tuned using Intel data
• SimplePower (Vijaykrishnan et al.)
• Adds bus and memory modeling, also I/O pads
• Look-up-tables (LUTs)
• Tempest (Cai Lim)
• Power density
• Chip-level thermal modeling
• No one data sensitivity, clock tree, global
  interconnect

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Typical Power-Performance Modeling
Technologyparameters
Micro-arch.config
Staticpower model
Cycle-accurateperformancemodel
Dynamicpowerestimation
activityfactors
cycle-by-cyclestatistics
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Power Basics

• P ½ACV2f ?AVIshort VIleak
• A activity factor
• C capacitance
• V dynamic voltage
• f frequency
• Ishort short-circuit current during switching
• Ileak leakage current

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Power Basics

• P ½ACV2f ?AVIshort VIleak P ACVDDVswingf
  ?AVIshort VIleak
• A activity factor
• C capacitance
• V dynamic voltage
• f frequency
• Ishort short-circuit current during switching
• ? duration of short-circuit current
• Ileak leakage current
• Why averages dont workBursty behavior, dI/dt,
  peak current, temperature

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Better Simulation Method
P ACVDDVswingf ?AVIshort Vileak sum over
all blocks
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Typical Power-Performance Modeling
Technologyparameters
Micro-arch.config
Staticpower model
Cycle-accurateperformancemodel
Dynamicpowerestimation
activityfactors
cycle-by-cyclestatistics
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Metrics

• What metrics do we care about?
• Execution time sec or IPC
• Energy (battery life) W
• Energy-delay product Ws
• Energy-delay2 product? Ws2
• Power density (temperature) W / mm2
• Temperature K or C
• DI/dt
• Peak power dissipation
• Might also care about these at finer
  granularitiesmicro-arch. blocks, decoders,
  circuits, etc.

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Basic Techniques for Power Efficiency

• Leakage turn things off (but you lose the data)
• Resize structures
• Turn off idle structures
• Turn off entries, eg cache decay
• 4T RAM cells?
• Dynamic reduce activity factors
• Clock gating
• Resize structures
• Utility predictor
• Throttle processor width (eg, fetch width)
• Filter caches
• Datapath resizing
• etc.

P ½ACV2f ?AVIshort VIleak
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Simulating Power for Greater Accuracy

• P ½ACV2f ?AVIshort VIleak
• In all these cases, we want to find relevant
  power-related parameters (esp. effective
  switching capacitance C)-- performance model
  provides A
• More detailed block-specific power
  information(circuit design style, etc.)
• Switching activity (Hamming distance)
• Interconnect (floorplanning, approx. area)
• Clock tree (H-tree vs. balanced H-tree)
• Random logic (empirical models)
• Busses, transactions, durations
  (pull-up/pull-down/hi-Z, read vs. write, etc.)

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Simulation Challenges

• Need leakage models - f(T)
• Need temperature models
• Eventually want to integrate all these into a
  fast simulator
• This is a research challenge in its own right