Architecture and Synthesis for Multi-Cycle Communication

1
Architecture and Synthesis for Multi-Cycle
Communication SOC Group, VLSICAD Lab Led by Jason
Cong Yiping Fan, Guoling Han, Xun Yang, Zhiru
Zhang
VLSI CAD LAB

• Motivation
• What is happening now
• Interconnect delays dominate the timing in DSM
  tech.
• What is about to happen
• Single-cycle full chip synchronization is no
  longer possible.

• Our Approach
• Regular Distributed Register (RDR)
  micro-architecture
• Highly regular
• Direct support of multi-cycle on-chip
  communication
• MCAS Architectural Synthesis for Multi-cycle
  Communication
• Integrated architectural synthesis (e.g. binding,
  scheduling) with physical planning
• Target at RDR architecture

MCAS vs. Conventional Flow MCAS achieves 31
clock period and 24 total latency reduction with
18 resource overhead and 11 clock cycle
increase on average.
MCAS vs. Synopsys Behavioral Compiler MCAS
achieves 21 clock period and 29 total latency
reduction on average, without area overhead.

• MCAS System
• Scheduling-driven placement
• Integrate list-scheduling with a SA-based global
  placement for minimizing the total latency.
• Employ net weighting technique to shorten the
  critical global connections.
• Placement-driven rescheduling rebinding
• Integrate force-directed list-scheduling with
  simultaneous rescheduling rebinding to further
  minimize the latency.

• RDR Architecture
• Distribute registers to each island
• Chose the island size such that local
  computation and communication in each island can
  be done in a single cycle
• Dintra-islandDlogicDopt-int?Dlogic2Dopt-int(Wi
  Hi)?T