Nested Procedure

1
Nested Procedure and Machine Language
Representation of Instruction
2

• Nested Procedure
• It is possible for a subroutine to jump to a
  second subroutine, then to a third subroutine and
  so on
• These are called nested subroutines because the
  second subroutine can be called within the first
  subroutine
• Lets consider the figure in the next slide

3
main
Sub1
sub2
Put address 0xC1C8 to ra jump to sub2
Put address 0xC124 to ra jump to sub1
. . .
jr ra
Push ra Push Registers to Stack. . jal sub2 .
. .. . Pop registers from stack Pop ra
(0xC124) jr ra
0xC1C4
jal sub1 . . .
0xC120
0xC1C8
0xC124
Jump to address of next instruction 0xC1C8
Jump to address of next instruction 0xC124
Stack after jump to sub2
Stack after jump to sub1
Stack before jump to sub1
Lower Address
sp
sp
Higher Address
content of mains registers content of ra
(0xC124)
content of mains registers content of ra
(0xC124)
sp
4

• The main program executes jal sub1 instruction
  which
• Puts address of next instruction (for example
  0xC124) into ra
• Jumps to the address that is shown by label sub1
• On the subroutine sub1,
• Saves the return address to the main program,
  which is in ra (0xC124), into the stack
• Saves main program registers into the stack
• During execution of sub1 another jal sub2
  instruction is encountered and this instruction
  causes
• Puts address of next instruction (for example
  0xC1C8) into ra
• Jumps to the address that is shown by label sub2
• Before ending subroutine sub2,
• Have jr ra instruction, go back to sub1

5
.data str1 .asciiz "\n In Main Before going to
subroutine" str2 .asciiz "\n In subroutine
1" str3 .asciiz "\n In subroutine
2" str4 .asciiz "\n Back to subroutine 1 after
subroutine 2 ends" str5 .asciiz "\n Back to the
main program after subroutine 1
ends" .text main li v0, 4 la a0,
str1 syscall jal subr1 put return address to
main into ra and jump to subr1 li v0,
4 la a0, str5 syscall j
exit subr1 sub sp, sp, 4 sw ra,
0(sp) li v0, 4 la a0, str2 syscall jal
subr2 put return address to subr1 into ra and
jump to subr2 li v0, 4 la a0,
str4 syscall lw ra, 0(sp) add sp, sp,
4 jr ra return to main routine subr2 li
v0, 4 la a0, str3 syscall jr
ra return to subr1 exit
This is an example of simple nested
subroutine It only shows how two subroutine are
created and how the control flows from the
main program to a subroutine1, from subroutine1
to subroutine2 and then goes back to the
main program
6

• This procedure can be continued
• The third subroutine can call a forth and so on
• Subroutines can be nested to any level provided
  there is enough room in the stack for saving
  arguments and return address, which means the
  stack does not grow beyond the understood ending
  addresses (See slide 11 from the last lecture)

7
Machine Language Representation of Instruction
8
Swap (int vm int k) int Temp temp
vk vk vk1 vk1 temp
High-level language program (in C)
Swap muli 2, 5, 4 add 2, 4, 2 lw 15, 0
(2) lw 16, 4(2) sw 16, 0(2) sw 15,
4(2) jr 31
Assembly language program (For MIPS)
Assembler
00000000101000010000000000011000 00000000100011100
001100000100001 10001100011000100000000000000000 1
0001100111100100000000000000100 101011001111001000
00000000000000 10101100011000100000000000000100 00
000011111000000000000000001000
Binary machine language program (for MIPS)
9

• Now we are ready to explain the way machines
  (computers) see instructions.
• A system program, known as assembler, transforms
  the assembly language instruction to series of
  0s, and 1s which are high and low signals
• So instructions are kept in the computer as a
  series of high and low electronic signal
• In fact, each piece of an instruction can be
  considered as an individual binary numbers
• To keep the MIPS processor simple and fast, all
  instructions fit in 32 bits
• Assembly instructions base on their operations
  and their operand (registers, immediate, address)
  can be mapped to three instruction layouts.

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Register Table
11
Register Table Cont
12
Instruction Code Table
13

• Each of these instruction layouts has different
  fields
• R-type format
• I-Type format
• J-Type format

6 bit 5bit 5 bit 5 bit 5
bit 6 bit
6 bit 5bit 5 bit
16 bit
6 bit 26 bit
14

• As we know, in MIPS assembly language, register
  s0 - s7 maps to 16th to 23rd registers in the
  processor and registers t0 to t7 map to 8th to
  15th registers in the processor
• Each operation add, sub, mult, div, j, jal, beq,
  .. has its own code (a binary number)

15

• First type of instruction layout R-type (register
  type)
• R-type is for operations that are using only
  registers as operands like sub, add, mult, div,
  mfhi, mflo, jr ra

6 bit 5bit 5 bit 5 bit 5
bit 6 bit

• op field (opcode) partially specifies what
  instruction is (note this field is equal to zero
  for R-type instruction
• rs field (source register) generally used to
  specify register containing first operand
• rt field (target register) generally used to
  specify register containing second operand
• rd field (destination register) generally used to
  specify register which receive the result of
  operation
• shamt field (shift amount). This field contains
  the amount a shift instruction will shift by. We
  wont use shift instruction in this course. So
  the shamt field would be 0 all the time.
• func field (function). This field contains a code
  which you can find in instruction code table. The
  code in this field, along with the code that used
  in opcode field, will exactly specifies the
  instruction (code that tells hardware to do
  addition, or subtraction or .)

16

• Example
• Write the machine instruction for this assembly
  instruction
• add t0, s1, s2
• By looking at the register table, we can find out
  the corresponding number to each register.
• t0 corresponds to 8 (rd field)
• s1 corresponds to 17 (rs field)
• s2 corresponds to 18 (rt field)
• Since the add instruction uses only registers,
  then it is R-type format
• Since it is R-type format, the op field would be
  0
• By looking at the instruction code table, the
  func code is 32 for the addition instruction

17

• Using these information
• add t0, s1, s2

6 bit 5bit 5 bit 5 bit 5
bit 6 bit
decimal representation
6 bit 5bit 5 bit 5 bit 5
bit 6 bit
Machine language instruction representation
6 bit 5bit 5 bit
5 bit 5 bit 6 bit
18

• Special Cases for R-type Format
• Some instructions that use registers as operand
  like mult, div, mfhi, mflo, j ra do not use
  all the fields of the R-type format
• mult and div have nothing in the rd field
  (destination register field). Since the
  destinations are hi and lo registers, in this
  case rd field would be 0.
• mfhi and mflo have nothing in the rs field
  (source register field) and rt field (target
  register). Therefore, rt and rs field will be
  0. These instructions move values from hi or
  lo registers and put them in destination
  registers (rd field).
• jr ra instruction has nothing in rt field
  (target register) and rd (destination
  register), So they are 0.

19

• Example
• Write the machine instruction for this assembly
  instruction
• mult s3, s4
• op field is 0 ,since it is R format
• rs field ( source register) first operand is s3
  which correspond to
• 19th register in the processor
• rt field ( target register) this field represents
  the second operand which is s4 and it
  corresponds to the 20th register in the
  processor
• rd field ( destination register) this field
  represents the result of operation register, in
  the case of mult instruction is 0.
• func field ( function ) contains code for mult
  instructions, which we know is 18 by checking the
  instruction code table.

20

• Using these information
• mult s3,s4

6 bit 5bit 5 bit 5 bit 5
bit 6 bit
decimal representation
6 bit 5bit 5 bit 5 bit 5
bit 6 bit
Machine language instruction representation
6 bit 5bit 5 bit
5 bit 5 bit 6 bit
21

• Example
• Write the machine instruction for this assembly
  instruction
• mfhi s1
• op field is 0, since it is R-type
• rs field ( source register) first operand is 0
  in the case of mfhi instruction
• rt field ( target register) this field represents
  the second operand which is 0 in the case of mfhi
  instruction
• rd field ( destination register) is for
  destination register which in this case is s1
  and correspond to 17th register in the processor
  field represent result of operation register
  that in case of mult instruction is 0
• func field ( function ) contains the code for
  mfhi instruction, which is 10 by looking at table

22

• Using these information
• mfhi s1

6 bit 5bit 5 bit 5 bit 5
bit 6 bit
decimal representation
6 bit 5bit 5 bit 5 bit 5
bit 6 bit
Machine language instruction representation
6 bit 5bit 5 bit
5 bit 5 bit 6 bit
23

• Example
• Write the machine instruction for this assembly
  instruction
• jr ra
• op field is 0, since it is R-type
• rs field (source register) first operand is ra
  which is 31st register in the processor
• rt field (target register) this field represents
  the second operand which is 0 in the case of mfhi
  instruction
• rd field (destination register) is for
  destination register which in this case is 0
• func field (function) is the field that contains
  code for jr instruction, which is 8 by looking
  at table

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• Using these information
• jr ra

6 bit 5bit 5 bit 5 bit 5
bit 6 bit
decimal representation
6 bit 5bit 5 bit 5 bit 5
bit 6 bit
Machine language instruction representation
6 bit 5bit 5 bit
5 bit 5 bit 6 bit