ASICs for HighEnergy Astrophysics: Instrument Design Considerations

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ASICs for High-Energy AstrophysicsInstrument
Design Considerations
Fiona Harrison Caltech
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What is an ASIC?
Application Specific Integrated Circuit (ASIC)
also referred to as Very Large Scale Integrated
Circuit (VLSI) A circuit custom-designed for a
specific application is integrated onto a single
silicon chip
16 pulse-height analysis chains for Si strip
detectors
Single pulse-height analysis chain for Si strip
detector
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Why ASIC Technology?
ASICs require Commercial chips are scarce and
often require modification Specialized expertise
to carry out a new, custom design Long
development periods Can be costly and have
schedule risk Advantages Power Enables
experiments with large numbers of
channels Minimizes heat dissipation for cooled
detectors Reduces spacecraft costs Size Enables
large channel count Makes new detector
architectures possible (ie small-pixels) Higher
spatial and spectral resolution (low capacitance)
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Power
The same analog circuit has intrinsically lower
power in an IC Power Power (input FET) Power
(secondary amp etc) Power proportional to
capacitance C(input) C(secondary) C(input) is
similar for hybrid and IC but C(secondary)
dominated by stray capacitance C(stray - IC) ltlt
C(stray - hybrid/PCB) - for fixed gain
bandwidth Typical C stray 10 pF analog
hybrid Typical C stray 10 fF IC -gt power
is generally dominated by secondary shaping, so
can be 100 times lower for IC (but in practice
other terms become important). In reality,
advantage is factor 20
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Power
Example PHA chain developed for Si strip
detectors at CIT hybrid version 120
mW/PHA combination hybrid/IC 40
mW/PHA CMOS ASIC IC 6 mW/PHA
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Size
ASICs are considerably smaller than hybrid with
identical function complex analog circuit
(shaping, discriminator, peak detect) can fit in
0.5mm x 0.5 mm This enables Instruments with
large numbers of channels New detector
architectures previously not possible small-pixel
solid state detectors Architectures with low
capacitance, enabling good spectral resolution
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Designing an ASIC
ASICs for some purposes are commercially
available, however optimum performance often
requires some modification Development time must
be factored into the mission schedule For
complex, demanding instrument configurations a
custom design is generally necessary Requires
experience and specific expertise Requires
significant development periods and generally
must begin well before phase C/D of the mission
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Steps in ASIC Development

• Foundry choice
• Influences basic (first-order) design
• i.e. availability of high-resistivity poly,
  multiple metal layers
• Process-dependent noise characteristics are
  important
• Determines prototyping options
• Some foundries are available through prototyping
  services (MOSIS) to reduce cost
• Some have full wafer run as only option
• Cost and schedule implications
• Factor in MOSIS schedule
• Must factor in 1-2 prototype runs (depending on
  complexity)
• Turnaround times typically 12 - 14 weeks

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Steps in ASIC Development
2. Design simulation accurate spice models,
software important diagnostic capability on-chip
precision scope buffer, test points critical to
incorporate in design 3. Layout critical for
analog circuits Parasitics, busing
important Layout is a specialized process
requiring significant attention In some ways is
easier ASIC is a 2-D truly planar situation.
Shielding is easier and inductance unimportant
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Steps in ASIC Development
4. Checking complete layout -gt schematic
comparison important (can cut traces but
difficult and expensive) Design rule checks
(process dependent) - also done at foundry 5.
Submission/fabrication Fabrication depends on
size of chip Options MOSIS (small) 4 mm2,
1k/mm2 (5 x 5mm max sensible) Foundry - wafer
run - 80 - 150 k (standard) 200 - 220 k (rad
hard) Mask costs dominate - additional per wafer
cost 0.5 - 10 k)
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Space Applications - Radiation Hardness

• Many ASICs are now rad hard by design
• Methodology
• Three tricks
• Guard banding (rings around transistors) for
  latchup tolerance
• edgeless transistors for high total dose
• Rad hard latch design for SEU immunity
• Can also go to a rad hard foundry process
  (expensive)

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HEFT/Con-X A Case Study
Parameter HEFT Con-X HXT pixel size (1/3Dqf
) 500 mm 480 mm energy band 20 - 100 keV 1
- 60 keV fwhm energy resolution lt 1 keV (68
keV) lt1.2 keV (6 keV) dimensions (FOVf) 2.1
cm x 2.1 cm 2.3 x 2.3 cm quantum
efficiency gt90 (20 - 100 keV) gt90 (6 -
60) (t CZT gt 1.5 mm) (t CZTgt 0.7
mm) trigger reqd yes yes max
countrate 100 ct/s/pixel 100
cts/s/pixel 500 ct/s/module 500
ct/s/module typ. countrate few ct/s/module few
ct/s/module time resolution 10 ms 10 ms

• Low-electronic noise for resolution (HEFT) and
  low threshold (ConX)
• Moderate-gt small pixels
• moderate countrate with good time resolution
• trigger required for shield readout

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HEFT VLSI Development - Case Study
VLSI technology makes a pixel detector
architecture possible - required to meet
performance requirements (resolution and
threshold)
CdZnTe pixel sensor high atomic number wide band
gap - no cryogens
Top contact contiguous Bottom contact (anode)
segmented into pixels Each contact is connected
via Indium bump bonding to a separate
readout 1-to-1 correspondence between readout
channels and pixels
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HEFT ASIC Development
46 x 23 array of readout channels on each
chip 50 microW/pixel Pixel size 500 microns
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HEFT ASIC Development
For flexibility and to mitigate risk in design
most logic functions are off-chip (readout mode,
etc)
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HEFT Detector Performance
NaI imaging PMT 1mm spatial resolution
500 mm CdZnTe detector/VLSI readout
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HEFT Development Schedule
Prototyping - Design - 6 months Layout - 3
months Prototype run - small single circuit to
test principle components - 3 months significant
diagnostic capability built in Testing - 2
months Production Design - 6 months Layout - 6
months Full-sized chip - wafer run 1 - 3 months
Testing - 3 months TOTAL 26 months Fixes
(optional) Design - 2 months Layout - 1
months Full-sized chip - wafer run 2
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Design Example - Swift Burst Array Telescope
Cut away drawing of BAT The D-shaped coded
aperture mask is 3 m2 with 5 mm pixels. The CZT
array is 5200 cm2 with 4 mm detectors. Graded-Z
shielding reduces the background due to cosmic
diffuse emission.
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Design Example - Swift BAT
Telescope Property Description Aperture
Coded mask Detecting Area 5200 cm2
Detector CdZnTe Detector Operation
Photon counting Field of View 2 sr
(partially-coded) Detection Elements 256
modules of 128 elements Detector Size 4
mm x 4 mm x 2 mm Telescope PSF 17 arcmin
Energy Range 15-150 keV
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BAT Detector Performance
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BAT ASIC Development Experience
Investigated both custom development and off the
shelf purchase Chose already-developed
commercial chip due to schedule Sacrifice some
performance and desired capability Possible
options available (at the time) ISGRI - chip
developed for Integral too difficult to
negotiate design modifications RENA (Tumer) -
did not exist, had not been fully prototyped IDE
(Norway) XA1 Identified a thermal stability
problem - made 3 design modifications, got second
version of chip
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BAT ASIC Development Experience
Total cost for 2 versions 93 k (500
parts) Cost with no modifications 30 k
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