Status of SPD electronics

1
Status of SPD electronics

• Review of ASIC runs
• PMT DC current problem
• RUN 4 whats new

Xavier Vilasís LHCb week May 2002 Calorimeter
Meeting
2
Review of ASIC runs

• RUN1 (Sep 2000)
• Test separate blocs
• 1 full channel
• RUN2 (Jun 2001 test beam)
• 4 full channels
• ECL vs CMOS output
• RUN3 (Jan 2002)
• New tunnable substractor
• 1 full channel with digital control
• On-chip DAC to program thresholds

3
PMT DC current problem
PMT supports only 100uA DC (18uA with actual
base) SPD at hottest point (10 occupancy)
64 channels 1 pC / MIP 0.1 / 25 ns 250 uA

• Solution
• Build a new base supporting 100 uA
• Reduce PMT gain (100 fC / MIP)
• Increase PMT load Resistor (150O ? 400O)
• Increase ASIC gain (factor 3)
• Decrease 1 MIP threshold by factor 2

4
RUN 4

• Sent 24-05-2002
• Contains
• 1 Complete processing channel
• Separate blocs digital control
• Works at 3.3 V to reduce power consumption
• RUN3 equivalent consumption for 8 channels 1.2W
• Estimated power consumption for 8 channels 0.6W
• All blocks have been redesigned from schematics
• Overall architecture remains
• Higher gain (x3) to meet PMT DC current limit
  requirements
• Fully differential preamplifier added before the
  integration stage
• Towards final prototype
• Will be tested Sep-Oct 2002
• November 2002 final prototype with 8 channels

5
RUN 4