ECE 4120 FixPt 1

1
Fixed-Point Computer Arithmetic

• ECE 4120 Fundamentals of Computer Design
• Dr. Roger L. Haggard, Associate Professor
• Department of Electrical and Computer Engineering
• Tennessee Technological University
• Spring 2004

2
Fixed / Floating Point Computer Arithmetic

• Number Representations
• Fixed Point - Both Integer and Fraction
• Floating Point
• Arithmetic Implementations ( - / )
• Fixed Point
• Floating Point

3
Fixed-Point - Integer (1)

• Assign N-bit binary string bn-1 bn-2 b1
  b0
• N bits Þ 2N values possible
• Unsigned Integer V (unsigned int) å bi2iEx
  10102 1010 0 lt V lt 2N - 1
• Signed Integer V (twos comp) -bN-1 2N-1 å
  bi2i -2N-1 lt V lt 2N-1 - 1Ex 10102
  -123 022 121 020 -8 2 -6 or
  -(0101 1) -0110 -6 ones comp 1

N-1 I 0
N-2 I 0
4
Fixed-Point - Integer (2)

• These bit strings are fixed-point INTEGERS
  because we assume the radix point at right of LSB
  for all numbers (e.g. 1011.)
• If the radix point is always assumed at another
  fixed position, we have a fixed-point non-integer
  system

5
Fixed-Point - Non-Integer (1)

• Assign N-bit binary string, with radix point p
  bits to left of LSB bn-1 bn-2
  b2 b1 b0 pN
  p2 p0 (fraction)
  (mixed) (integer)
• Twos Comp. Fixed Point V (Fixed pt., Twos
  comp.) V (twos comp) 2-p -bN-1
  2N-p-1 å bi2i-p Ex 1010 (twos comp.)
  -6 1010 (Fixed pt. Twos comp.) 10.10
  (assuming p2) V -62-2 -6/4
  -1.5 or V -124-2-1 020 12-1 02-2
  -2 0 .5 0 -1.5

N-2 I 0
6
Fixed-Point - Non-Integer (2)

• Compared to INTEGER arithmetic
• Add/Sub operates the SAME
• Mul/Div operates the SAME, but must correct the
  radix point

7
Number System Characteristics

• Important characteristic of a number system is
  its granularity - the difference between
  adjacent values Dr LSB value
• Integers (p 0) Dr 1 000. 001.
• Fixed Pt (p 1) Dr 1/2 00.0 00.1
• Fixed Pt (p 2) Dr 1/4 0.00 0.01
• \ Dr 2-p (constant for any numerical value V)
• Fixed Point used where
• Dynamic range is limited
• Use of low cost, high speed integer hardware
  desired

8
Other Fixed-Point Signed Representations(Beside
2s complement)

• 1s complement See text
• Signed magnitude
• MSB sign bit (1 neg, 0 pos)
• other bits magnitude (positive) Ex 1011
  -011 -3
• Excess system
• S V E
• S stored representation
• V real value
• E fixed excess value

9
Example Excess 8 Code, 4 Bit Number
10
Fixed-Point Number System Summary

• N-bit binary string can represent 2N
  objects numbers, characters, events, things
• Assumptions determine actual value of bit string
• Assumptions affect the hardware design
• Fixed point implies
• constant Dr
• limited range of values
• mult/div must watch shifts in radix point
• Various coding methods possible Unsigned,
  Signed 1s 2s complement, Signed Mag, Excess

11
Fixed-Point Implementation -The Arithmetic Unit

• Hardware Circuits for fixed-point Add, Subtract,
  Multiply, Divide
• First, Addition and Subtraction of Fixed-Point
  Numbers
• Integer, Fraction, or Mixed Integer/Fraction all
  use same hardware
• Only difference is the assumed position (p) of
  radix point

12
Full Adder
Ai
Bi
Ci-1
A B CIN Full Adder (FA) COUT F
Ci
Fi
F AÅ B Å CIN COUT AB ACIN BCIN \ Max
delay 2 gate levels \ TFA 2 TG
13
Cascade for Multi-bit Adder Ripple-carry Adder
(RCA)

• Simplest Method
• Slowest Method
• TRCA N 2 TG

14
Subtraction - Two Methods

• Full Subtractor, Cascade for Ripple-Borrow
  Subtractor
• 2s Complement Addition, Cascade for Ripple-Carry
  Subtractor
• A - B A (-B)
• -B B1
• So, A - B A B 1
• TRCS N 2 TG TG

B0
B1
B2
A0
A1
A2
1
FA
FA
FA
C0
C1
C2
F0
F1
F2
15
Look Ahead Carry (1)

• Slow because each stage waits on COUT from
  previous stage
• All Fi, Ci are combinational functions of all Ai,
  Bi, C-1

16
Look Ahead Carry (2)
2nd stage F1 A1 Å B1 Å C0 C1 A1B1 A1C0
B1C0 A1B1 (A1 B1) C0
G1 P1 G0 P0C -1 G1 P1G0 P1P0C
-1 f (Ai, Bi, C -1)
3rd stage F2 A2 Å B2 Å C1 C2 G2
P2C1 G2 P2G1 P1C0 G2
P2G1 P2P1G0 P2P1P0C-1 f (Ai, Bi, C -1)
17
Look Ahead Carry (3)
General Equations 1 level Gi AiBi 1
level Pi Ai Bi 3 levels Ci Gi Pi Ci
-1 (Expand recursively until reach C-1) 4
levels Fi Ai Å Bi Å Ci-1
Fi f (Ai, Bi, Ci-1) Ai Å Bi Å Ci-1 Ci f
(Ai, Bi, C-1) Gi Pi Gi-1 Pi Pi-1 Gi-2
Pi Pi-1P0 C -1
All outputs possible in 2 gate delays, But much
simpler logic with 3 or 4 gate delays, so \TADD
4TG, NOT TADD N 2 TG !
18
Look Ahead Carry Adder (LACA)
1) Fully integrated circuit (74S283) OR 2)
Separate adder carry generator (74S181
74S182)
C-1
A3
B3
A2
B2
A1
B1
A0
B0
LACA
LACA
LACA
LACA
F3
F2
F1
F0
19
Look Ahead Carry Cascading
1) Ripple Carry between LACGs, or
C-1
LACG
LACG
GG GP CIN
GG GP CIN
LACG
CIN
C3
C3
20
Look Ahead Carry Cascading
2) Hierarchy of LACGs
C-1
LACG
LACG
GG GP CIN
GG GP CIN
LACG
CIN
C3
C3
21
Group Carry Generate and Carry Propagate

• GG Þ Cout true regardless of Cin
• GP Þ Cout true IF Cin is true
• \ Cout GG GP Cin

B
A
2
2
2 bit CLA Adder
GG
C-1
GP
Cout C1
2
F
22
Fixed-point Multiplication

• Unsigned N-bit multiplication 2N-bit product

A - multiplicand x B - multiplier P
- product

• If signed values,
• (1) Convert to magnitude, do unsigned
  multiplication, convert back to signed, OR
• (2) Use different multiplication
  algorithms Beyond our scope

23
Fixed-point Multiplication Methods

• Iterative (Sequential) - slower, cheaper, less
  hardware
• Repeated Addition
• Shift and Add
• Direct (Combinational) - faster, much more
  hardware

24
Iterative Multiplication Repeated Addition
Method

• Repeated Addition Add the multiplicand,
  multiplier times
• Algorithm
• Product 0
• While Multiplier gt 0 do
• Product Product Multiplicand
• Multiplier Multiplier - 1
• End While

25
Repeated Addition Example
Example 5 5 101 x 3 Þ 5 Þ x
011 15 5 001111 15
Time Product Multiplier Initial 000
000 011 gt0 101 1 000101 010 gt0 101
2 001010 001 gt0 101 3 001111 000 0
DONE
26
Repeated Addition Block Diagram
Multiplicand
Multiplier
Zero
N
N
N
2N
2N
MPLD
N-bit DownCounter
A B 2N-bit Adder F
MPCNT
CLK
MP 0
2N
2N-bit
/PLD
ControlFSM
CLK
D LD 2N-bit Product Reg Q
CLR
CLK
/PCLR
2N
Product Reg
2N
GO
DONE
Product
27
Repeated Addition Timing

• Total Execution TimeTMUL (2N - 1) x TCYCLE
• WhereTCYCLE ³ TCQ TADD TSU

28
Iterative Multiplication Shift and Add Method
(1)
3-bit Binary Example A2 A1
A0 Multiplicand x B2
B1 B0 Multiplier A2B0 A1B0 A0B0
PP0 A2B1 A1B1 A0B1 PP1 A2B2
A1B2 A0B2
PP2 P5 P4 P3 P2 P1 P0 Product
29
Shift and Add Method (2)
Formula for 3-bit Multiply Prod PP0 PP1
PP2 A x B0 x 20 A x B1 x 21
A x B2 x 22
30
Shift and Add Algorithm
Algorithm Repeat forever Wait until G0 1
Prod 0 Done False Bits_Left N MPSR
Mplier While Bits_left gt 0 do If
Mplier(0) 1 then ProdMSH ProdMSH
Mcand Else ProdMSH ProdMSH 0 End
if Bits_left Bits_left -1 Shift_Right (Prod
MPSR) End While Done True End Repeat
31
Shift and Add - 3 bit Example
Mcand Bits_left Multiplier
Product
1 1 0
Example 110 x 011
1 1 0 1 1 0 0 0 0
_ 0 1 0 0 1 0
3
0 0 0 0 0 0
0 1 1
Add
1 1 0
1 1 0 0 0 0
0
0 1 1 0 0 0
0 0 1
2
1 1 0
Add
0 0 1 0 0 0
1
Or add Zero!
1 0 0 1 0 0
0 0 0
1
No Add
0 1 0 0 1 0
0 0 0
0
32
Shift and Add Block Diagram (1)
Mplier 70
CLK
8
MLD
FSM Control
LD A - H QH CLK 8-bit shift
register SH MPSR
worst-case path
MSH
Mcand 70
GO
8
DONE
8
0 or Mcand
8
NLD
A B Cout F
8 bit adder
NCNT
7
N 0
9 bits
PCLR
CLR D15 D14-7 D6-0
PROD LD
16-bit register CLK Q
PLD
16
Q7-1
Q15-8
16
Prod150
33
Shift and Add Block Diagram (2)
N
NLD
Multiplier Timing
Bits_left
NCNT
N 0
16 15 14 13 12 11 10 9
8 7 6 5 4 3 2
1 0
C F7 F6 F5 F4 F3 F2 F1 F0 Q7
Q6 Q5 Q4 Q3 Q2 Q1 Q0
Load and Shift Right
15 14 13 12 11 10 9 8
7 6 5 4 3 2
1 0
C F7 F6 F5 F4 F3 F2 F1 F0 Q7
Q6 Q5 Q4 Q3 Q2 Q1
PROD reg
34
Shift and Add - Controller Design (1)
Reset
Q2Q1Q0
100
WAITGO
Done
Go
F
T
INIT
010
PCLR, NLD, MLD
T
F
N 0
NCNT, PLD, MSH
001
MULT
35
Shift and Add - Controller Design (2)
W
I
M
M
M
W
CLK
0 0 2
1 0 0
NLD
NCNT
PLD
N 0
DONE
36
Shift and Add - Controller Design (3)
37
Direct Multiplication Methods

• Much faster, but much more logic (than iterative)
• Product is a combinational function of operands
• Form all partial product bits (in one TG)
• Add N Partial Products with N-1 adders in
  series(so time (N - 1) TADD)

38
Direct Multiplication Terminology
A3 A2
A1 A0
x B3 B2 B1 B0
R03 R02 R01 R00
PP0 R13 R12
R11 R10 PP1
R23 R22 R21 R20
PP2
R33 R32 R31 R30
PP3 P7 P6
P5 P4 P3 P2 P1
P0 Prod



where R i j Bi A j and PPi Ri,N-1 Ri,N-2
Ri,N-3 ... Ri,0
N 2
39
Direct Multiplication - General Structure
A
B
PP Generators
PP
Various methods possible
PP Adders
Prod
40
Direct Multiplication - Linear Array (1)
N bit
P P G E N
PP0 PP1 PP2 PP3

4
A
N bit
N bit
B

4

2N bit Product
Note TADD 2NTG if RCA or 4TG if
LACA
41
Direct Multiplication - Linear Array (2)
R10
R01
R12
R03
R11
R02
R13
0
R00
A B Cin Cout F


2
6
4
8
R22
R21
R20
R23
5
7
3




11
9
7
5
R30
R31
R32
R33
10
8
6




12
10
8
13
14
11
9
7
P6
P5
P4
P3
P2
P1
P0
P7
Note Numbers show delay in TG
42
Direct Multiplication - Linear Array (3)

• TMULRCA 2N (N-2)3 TG 5N - 6 TG

43
Direct Multiplication - Tree
N bit
P P G E N
PP0 PP1 PP2 PP3

4
N bit
A

2N bit Product
B
4

Tmul Less than linear array for large N
44
Direct Multiplication - Carry-Save Adder (1)

• Dont propagate carries across each PP row
• Save till last addition in each column.
• Carry-Save Adder (CSA) Multiplier
• Faster than RCA
• Simpler (much less logic) than LACA

45
Direct Multiplication - Carry-Save Adder (2)
R03
R02
R10
R01
R20
R11
R22
R13
R21
R12
R00
0
A B Cin Cout F
0
FA


CSA
2
2
2
1
1
1
R32
R31
R30
R23
2
0
1




CSA
4
4
5
3
4
3
3
4
R33




RCA
10
8
6
9
7
5
11
12
P4
P3
P1
P0
P5
P2
P7
P6
Note Numbers show delay in TG
46
Direct Multiplication - Carry-Save Adder (3)

• TMULCSA (2N - 4 2N) TG
• (4N - 4) TG
• Faster than TMULRCA (5N - 6) TG

47
Fixed-point Division

• Unsigned N-bit division 2N-bit dividend and
  N-bit divisor, quotient, remainder

Quotient Remainder Divisor Dividend

• If signed values,
• (1) Convert to magnitude, do unsigned division,
  convert back to signed, OR
• (2) Use different division algorithms Beyond
  our scope

48
Fixed-point Division Methods

• Iterative (Sequential) - slower, cheaper, less
  hardware
• Repeated Subtraction
• Shift and Subtract
• Iterative Approximation by Multiplication Beyond
  our scope

49
Iterative Division Repeated Subtraction Method

• Repeated Subtraction Subtract the divisor from
  the dividend, until remainder goes negative, then
  backup one step for the final remainder the
  quotient is the number of successful
  subtractions.
• Algorithm
• Remainder Dividend Quotient 0
• While Remainder gt 0 do
• Temp Remainder - Divisor
• IF Temp gt 0 THEN
• Remainder Temp Quotient Quotient 1
• ENDIF
• End While

50
Repeated Subtraction Method - Example
33 - 6 Quotient Execution Time? 27
1 - 6 21 2 - 6 15 3 - 6 9
4 - 6 3 5 - 6 - 3 STOP! 6
3 R 5 Q
51
Iterative DivisionShift and Subtract Method

• Based on the grade-school arithmetic process
• Guess next Qi digit
• Mult Qi x Divisor
• See if Dividend - Qi x Divisor lt 0
• If NOT, then keep this Qi and start next digit
• Else reduce Qi and try again

52
Shift and Subtract Method - Example
53
Shift and Subtract Method - Block Diagram
Dividend
2N
Hi
Lo
N
Divisor
Mux
N
N1
N
Qbit
Ds
R
Q
N1
N1
N1
Partial Remainder (PR)
54
Shift and Subtract Method - Algorithm
Ds Divisor, RQ Dividend Count N While
Count gt 0 do Shift Left (RQ) PR R - Ds IF PR
³ 0 then keep R PR Qbit 1 Else
undo Qbit 0 Endif Count Count - 1 End
While
55
Shift and Subtract Method - Step-by-step
Count Ds R Q CLK 4 CLK SL Sub
1 1 0 1 0 1 1 1 1
0 Neg CLK 3 Ld Q0 CLK SL Sub
1 1 0 1 0 0 0 0 1
0 Pos CLK 2 Ld R, Q0 CLK SL Sub
1 1 0 1 0 1 1 1 1
0 Neg CLK 1 Ld Q0 CLK SL Sub
1 1 0 1 0 0 0 0 1
1 Pos CLK 0 Ld R, Q0
0 1 1 0
0 0 0 1 0
0 0 0 1
0 0 1 0 0
0 0 1
0 0 1 0 0
0 0 1 0
0 1 0 0 0
0 1 0
0 0 0 1 0
0 1 0 1
0 0 1 0 0
1 0 1
0 0 1 0 0
1 0 1 0
0 1 0 0 1
0 1 0
0 0 0 1 1
0 1 0 1
Requires Ds gt R
56
Shift and Subtract Method - 16-bit Hardware
Databus (15-0)
16
16
16
PR (15 - 0)
DividendMSH
Divisor
DividendLSH
B A 16 bit 2 to 1
16
16
16
Ds
Q
R
16 bit Reg
16 bit PIPO SR
16 bit PIPO SR
16
16
16
16
B A 16 bit Add
16 bit 3S Driver
16 bit 3S Driver
1
16
16
PR (15 - 0)
Databus (15-0)
16