Power Analysis and Estimation for Digital CMOS Circuits

1
Power Analysis and Estimation for
Digital CMOS Circuits
Jins Davis Alexander Vishwani D. Agrawal
Department of Electrical and Computer
Engineering Auburn University, AL 36849 USA
2
Motivation For This Work.

• An accurate and efficient power estimation tool
  for CMOS circuits.
• To estimate and separate the different components
  of power dissipation in a single packaged tool.
• Knowledge of components of power is useful in
  design decisions and optimization.
• Most existing tools estimate the total power or
  are specific to a particular power component.

3
Outline

• Existing Power analysis Tools.
• Various power components.
• Dynamic Power Estimation.
• Leakage (static) power estimation.
• Short circuit power estimation.
• Experimental Results.
• Future Work.
• Conclusion.

4
Some Power Analysis Tools and Techniques.

• PowerMill transistor level simulator for
  simulation of current and power from Synopsys.
• WattWatcher RTL level power estimator from
  Sente.
• PowerPlay dynamic power estimator based on
  logic simulation.
• Crest pattern independent current estimator.
• McPower- monte carlo approach to power
  estimation.
• Spice Simulators Mentor Graphics tools like
  Mach PA, ELDO simulator, Silvaco SmartSpice, etc.

5
Components of Power Dissipation.

• Dynamic
• Power due to Signal transitions.
• Logic power (due to logic transitions).
• Glitch power (due to glitches).
• Short Circuit component.
• Static
• Leakage power (due to leakage currents).
• Clock Power

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Power components.
Dynamic power
Leakage power
VDD
Ron
Short circuit power
vi (t)
vo(t)
CL
Rlarge
Ground
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Dynamic Power

• Depends on the switching activity of the gate and
  the load capacitance at the output node
  (switching capacitance).
• Supply Voltage and clock frequency.
• Dynamic power S 0.5 ai fclk CLi VDD2
• All gates i
• where fclk clock frequency
• ai activity factor of gate i
• CLi load capacitance of gate i

8
Dynamic power estimation.

• Calculation of logic transitions (events) by
  means of logic simulation.
• Event driven simulation algorithm used.
• Calculate energy dissipated for each event for
  every gate.
• Average dynamic power
• Total energy/Analysis
  period.

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Event driven Circular Time Stack
max
t0
Event link-list
1
2
3
4
5
6
7
10
Leakage power

• Majority of leakage dissipation is due to sub
  threshold leakage current.

VDD
IG
Ground
R
n
n
Isub
IPT
ID
IGIDL
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Sub threshold current.

• Isub µ0 Cox (W/L) Vt2 exp(VGS-VTH)/nVt
  (1 - exp(-VDS/Vt)
• where µ0 effective carrier mobility
• Cox gate oxide capacitance per unit area
• L channel length
• W gate width
• Vt kT/q thermal voltage
• n a technology parameter

12
Leakage power estimation.

• Leakage power is input vector dependent.
• Analyze which transistors of the gate are in ON
  state or OFF state during steady state analysis.
• Used BSIM3V3 spice models for calculation of
  threshold voltage, sub threshold currents for
  nMOS and pMOS transistors.
• Weighted time estimation of how long each
  transistor is in OFF state during the entire
  simulation period.

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Example of NAND Gate.
VDD
On
Off
On
Off
On
Off
0
0
1
Off
On
Off
0
1
1
On
On
Off
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Short Circuit Power.

• Short circuit current flows during the time when
  both transistors are in ON state.
• It depends on the rise or fall times of the input
  waveform.
• It also depends on the load output capacitance.
  Decreases for larger output load capacitance.
• The peak short circuit current occurs at the time
  when the transistor switching off goes from
  linear to saturation region.

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Short Circuit Current, isc(t)
VDD - VTp
V2
Volt
Vi(t)
Vo(t)
VTn
0
Iscmaxf
isc(t)
Amp
Time (ns)
t1
t3
t2
1
0
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Short circuit current calculation.
VDD
Rlarge
isc(t)
vi (t)
vo(t)
CL
Ron
tr
iC(t)
tf
Ground
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Short Circuit Modeling

• Ip(T1) VDD2 Kp(Vin 1 p )(Vout 1)0.5(Vout
  1)2
• Ip(T2) VDD2 0.5Kp (Vin 1 p )2
• where T1 t2 t1
• T2 t3 t2
• Kp pMOS gain factor.
• p Vtp/VDD

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Short Circuit Modeling.
Reference Wang, Q. and Vrudhula, S. B. K., "On
short circuit power estimation of CMOS
inverters," Proc. International Conference on
Computer Design (ICCD98), Oct 1998, pp. 70-75.
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Experimental Results (Average Power Dissipation
for 1000 Random Vectors)
Circuit Name Dynamic Power (µW) Logic Power (µW) Glitch Power (µW) Leakage Power (µW) Short Circuit (pW) Total Power (µW) CPU Time in secs
c432 1989.4 1031.3 958.1 0.0178 0.47 1989.42 15.3
c499 2452.5 1356.7 1095.8 0.0287 1.19 2452.56 22.5
c880 2720.0 1632.9 1087.0 0.0396 0.09 2720.04 37.1
c1355 8847.7 3039.2 5808.5 0.0577 2.84 8847.71 38.7
c1908 17292.3 5891.2 11401.0 0.1045 0.35 17292.43 130.2
c2670 15531.2 7373.5 8157.8 0.1024 1.29 15531.34 98.31
c5315 44921.8 18626.4 26295.4 0.2263 31.26 44922.10 437.2
c7552 66953.6 25341.3 41612.3 0.3182 43.21 66953.90 409.3

• Sun Ultra Workstation

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A Few Observations.

• If a gate has a greater fan-out , its dynamic
  power dissipation will increase. However the
  total dynamic dissipation increase will depend on
  the switching activity of the gate.
• A gate whose input node has a greater fan-out,
  will have an increase in short circuit power as
  the input rise or fall time to that gate will be
  higher as observed in circuits like c432.
• A gate with a bigger fan- out can increase short
  circuit power dissipation only if it causes an
  event at its fan- out gates. This phenomenon can
  be seen while comparing circuits c1908 and c2670.

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Experimental Results (Maximum and Minimum Power
Components)
Circuit Name Dynamic Power in µW Dynamic Power in µW Logic Power in µW Logic Power in µW Glitch Power in µW Glitch Power in µW Leakage Power in µW Leakage Power in µW
Max Min Max Min Max Min Max Min
c432 6657.5 419.05 1763.95 192.79 5929.59 0.00 0.0206 0.0144
c499 4084.5 594.33 2197.25 321.73 3277.46 0.00 0.0389 0.0222
c880 6177.3 905.99 2669.14 666.99 4535.64 0.00 0.0480 0.0328
c1355 15765.7 3388.54 4265.47 1508.90 12411.50 830.86 0.0634 0.0485
c1908 39646.4 5143.36 8554.57 2675.87 32097.70 1437.40 0.1169 0.0812
c2670 32892.6 5809.80 10437.50 4331.92 23572.30 1406.87 0.1075 0.0896
c5315 69993.3 25367.50 24560.70 12607.00 50099.70 8715.63 0.2458 0.1856
c7552 116104.0 28823.60 32611.60 15398.50 88828.30 9699.80 0.3404 0.2791
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Histogram for c7552 (1000 Random Vectors)
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Investigation of c7552 circuit

• The circuit produces a large number of glitches.
  Almost 66 of the total events are found to be
  glitches.
• Analysis of NAND gate 3718 showed that for a 1
  to 0 transition, the gate undergoes 22 extra
  transitions (glitches) before settling to steady
  state 0.

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Ongoing Work

• Estimation of clock power (power dissipated in
  clock trees or clock buffer circuits).
• Estimation of power in sequential and scan
  circuits.
• Spice validation of results at gate level.

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Conclusion

• This work discusses the techniques used for the
  efficient estimation of power in CMOS circuits.
• The tool successfully does a gate level logic
  simulation and separates different power
  components.
• Future work involves validation of results
  through Spice simulation of smaller circuits.

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• THANK YOU..