Status of the electronics systems of the MEG experiment

1
Status of the electronics systems of the MEG
experiment
2
Electronic chain
3
DAQ and control
Ancillary system
3 crates
6 crates
4
HV
5
HV

• Active down regulation of an external HV supply
• PSI design
• 10 chn per board
• 180 chn per 3 HE crate
• Back side connector
• Total of 6 crates

• 4 different requirements
• Lxe 1000V , 100 uA
• TC bars 2400V, 1 mA
• TC curved 500V, lt1 uA
• DC 2400V, 1 uA
• Commercial HV supplies delivered
• Mass production in progress
• Installation in September

6
Splitters
7
Splitter layout
Trigger or DRS

• ERNI high bandwidth output connector
• crosstalk with ERNI connector plus 2m cable is
  0.6

Input
DRS
Trigger
Power
8
Backplane layout

• Test circuit was implemented on backplane
• Debug completed
• PCB production in progress, mounting in house

9
Crates

• Mechanic parts and fans delivered
• Power supplies delivered and tested

Frontal panel
Back panel
Output (5V-36A)
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Cables

• Inputs
• Single coaxial cable (RG178 9m long) bundled
  into a polyester braided sleeve
• Negligible crosstalk between cables.

• DRS outputs
• High bandwidth output (DRS)
• high density twisted pairs cable (0.68 pitch) 2 m
  long with one flat zone in the middle (Amphenol
  SPECTRASTRIP 68p)

• Trigger outputs
• Low density twisted pairs cable (1.27 pitch) 2 m
  long with 2 flat zone (3M 34p/10p)

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Splitter Summary

• Splitter
• first prototype finished in may successfully
• PCB production started the first of June
• PCB production time one month
• Component procurement in progress
• Board mounting 2 weeks end of July
• Board test 1 week
• Boards ready by the beginning of September
• Backplane
• Crates and power supply delivered
• backplane production in Lecce
• Cables
• Trigger cables ready
• LXe cables in production
• DRS cables in production
• Installation
• Foreseen between September 5 and 20

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TC
13
PMT ramp generator
B
to Splitter
Analog signals to DRS and trigger
PMT
B
S
TC Analog Sign. Monitor
Passive Splitter
RAMP GEN.
D/D
6U Eurocards boards 8 boards
to Splitters
Signals to DRS
Dual Threshold OR Constant Fraction OR Leading
edge discriminator
NIM Signal for any possible use
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Production

• PMT ramp generator
• Design of the final boards in progress
• Mass production September (?)
• system delivery 8 boards October (?)
• APD pre amplifiers
• First prototype with problems on IC and cross
  talk
• Second prototype design and test completed
• Mass production and test in progress
• system delivery end of July
• APD hit registers
• board design completed
• Production and test in progress
• system delivery (6 boards 6U VME) end of July

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Trigger
16
TriggerBoards
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System test

• 4 Type1
• 2 Type2
• 2 Ancillary
• Synchronous operation
• No transmission errors

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Splitter-Type1 connection
Alpha and cosmic muon events from the Pisa
facility
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Number of boards summary table
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Number of boards status
Done !

• Boards Type1
• 48 funded
• 36 needed
• 40 delivered
• 8 not completely mounted
• 40 tested

Done !

• Boards Type2
• 10 funded
• 5 needed
• 10 delivered
• 10 tested

• Front-End Boards
• 800 funded
• 576 needed
• 800 delivered
• 320 tested

• Boards Ancill
• 8 funded
• 4 needed
• 4 delivered
• 4 not completely mounted
• 2 tested

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Firmware V1.0 Present Status

• Type1 VIRTEX II- PRO (XC2VP20-7-FF1152) ?
• Type1-0 LXe front face ?
• Type1-1 LXe lateral faces ?
• Type1-2 LXe top,bottom and back face ?
• Type1-3 TC bars ?
• Type1-4 TC fibers ?
• Type1-5 DC ?
• Type1-6 Auxiliary devices ?
• Type1-7 LXe back face x
• Type2 VIRTEX II- PRO (XC2VP40-7-FF1152) ?
• Type2-0 Final Level completed ? ?
• Type2-1 LXe frontup/down faces ?
• Type2-2 LXe lateral faces ?
• Type2-3 TC ?

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Board Type3
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Board Type3
Modified Type1 boards to produce an auxiliary
digitization of the LXe signals

• Type3 board 32 channels
• Number of boards for the LXe lateral sides(612
  chn) 20
• Boards design ready
• PCB prototype end of July
• Component delivery (12 weeks) beginning of
  September
• Test September
• Production October
• Installation end of October

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Comments on trigger

• Installation
• Ready any time from beginning of Jul. to end of
  Aug.
• Should follow the NaI moving system
• Should precede the electronic integration Sep.
• DAQ computers
• Configuration
• Baseline version V1.0 written
• Needs tuning, at least 1 month during
  purification
• Needs analysis tools, under development
• Documentation
• Hardware register list available
• Almost available for Type1
• In progress for Type2

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DRS
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DRS

• DRS2 available for all channels
• New PMC card finished
• Reduced noise 1.2 mV ? 0.5 mV RMS
• Self-calibration on card
• Mass production started
• cards expected in August
• PSI GPVME boards in production
• Delivery end of August

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DRS2 issues
Issue Solution DRS2 DRS3
Voltage nonlinearity Calibration with cubic splines in Front-end ?
Clock nonlinearity Time calibration frequency regulation ?
Cross talk 1 _at_ 7ns risetime Redesign of CMC card with ERNI 68-pin connector and interleaved ground lines ?
Temperature dependence - Calibration maybe possible to some extend- Keep electronics temperature constant- On-chip temperature compensation ?(?) ?
Self-heating of cells - Only use small signals (lt0.5 V)- On-chip temperature compensation (?) ?
Ghost pulses - Veto trigger 5us after cosmic or LED event- Veto trigger after other calorimeter hits?- Record 2us calorimeter history in each event?- Redesign sampling cell ? ?? ?
All issues could be resolved as planned
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DRS3

• DRS3 design finished
• Prototypes expected in August
• Tests foreseen at the end of the year

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DRS3 layout

• Smaller standard cells
• Totally gt 600,000 transistors
• Smaller package (QFP64)
• 12 channels/chip
• ROI readout and parallel readout to reduced dead
  time230 ms ? 50 ms ? 5 ms

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DRS and Trigger Crates
20 cm
Issue Splitter rack cannot be accessed easily
from back side!
Power distribution box
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DAQ cluster
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DAQ Cluster Layout
/home/meg -- root lt- ROOTSYS --
midas lt- MIDASSYS -- mxml -- rome
lt- ROMESYS -- meg lt- MEGSYS
-- meganalyzer -- megbartender
-- megmc -- online
-- drivers -- eventbuilder
-- frontend --
slowcontrol -- bts
-- calorimeter -- scfe
-- trigger -- VPC
80 GB System Disk RAID 1 (Mirror)
VME-Interface
Front-End 1
80 GB System Disk RAID 1 (Mirror)
VME-Interface
Front-End 2
. . .
NFS
80 GB System Disk RAID 1 (Mirror)
SC-FE
1.2 TG Data Disk RAID 5
/home/meg
Data rate 100 MB/s
Back-End
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Front-end computers
GBit Switch
Front-end 1

• Two DAQ computer installed with DAQ software
• Remaining computers delivered
• Installation end of July

Back-end1.2 TB disk
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Offline Cluster
15 x 500 GB SATA
Sun Fire x4100 quad core 4 GB
Sun Fire x4100 quad core 4 GB
Fiber Channel Switch
Sun Fire x4100 quad core 4 GB
GBit Ethernet
Sun Fire x4100 quad core 4 GB
Sun Fire x4100 quad core 4 GB

• Ordered on June 14th 20 cores 30 TB disk
• Easily extensible
• Redundancy through GFS/GPFS file systems
• GBit link to online cluster requested

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Slow control
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SCS-2000

• Replaces SCS-1001 unit
• 64 I/O lines (analog, digital, opto-coupler,
  PT100, etc.)
• Outputs stable during CPU firmware upgrade (? BTS
  control)
• Soft fuse
• LED pulser (40 lines, computer controllable)

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BTS slowcontrol

• Slowcontrol back-end to MSCB slow control units
• Integrated in MIDAS history system
• Monitoring and control though MIDAS web pages
• More pages added as SC equipment gets operational

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MIDAS history
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Conclusions

• All the key elements of the electronic system are
  available for integration in September
• Some parts will arrive with 1 month delay

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Rack space