Analog VLSI Bayesian Networks for Signal Processing

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Analog VLSI Bayesian Networksfor Signal
Processing

• Benjamin Vigoda, MIT Media Lab

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Logic Gates
Probability Gates
SoftXOR
XOR
0 0 00 1 11 0 11 1 0
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Noise Lock Loop (NLL)
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Bayes2Gates Compiler
Waveform probing commands .probe .options
probefilename"D probesdbfile"D
probetopmodule"3 softxors" .SUBCKT softxor p_x0
p_x1 p_y0 p_y1 p_z0 p_z1 GND Vdd M4 N5 p_y1 N7
GND NMOS_49 W'48l' L'4l' AS'40ll'
AD'40ll' PS'24l' PD'24l' M1 M8 N1 p_y0 N7
GND NMOS_49 W'48l' L'4l' AS'40ll'
AD'40ll' PS'24l' PD'24l' M1 M7 N8 p_y1 N1
GND NMOS_49 W'48l' L'4l' AS'40ll'
AD'40ll' PS'24l' PD'24l' M1 M3 N8 p_y0 N5
GND NMOS_49 W'48l' L'4l' AS'40ll'
AD'40ll' PS'24l' PD'24l' M1 M9 GND p_x1
N1 GND NMOS_49 W'48l' L'4l' AS'40ll'
AD'40ll' PS'24l' PD'24l' M1 M6 N5 p_x0
GND GND NMOS_49 W'48l' L'4l' AS'40ll'
AD'40ll' PS'24l' PD'24l' M1 M12 p_z1 N7
Vdd N6 PMOS_49 W'48l' L'10l' AS'66ll'
AD'66ll' PS'60l' PD'60l' M1 M11 Vdd N7 N7
N2 PMOS_49 W'48l' L'10l' AS'66ll'
AD'66ll' PS'60l' PD'60l' M1 .ENDS Main
circuit 3 softxors .tran 1n 1600n .include
Mami_15.md .options abstol1e-15 .param l0.8u R1
N1 GND 50 TC0.0, 0.0 R2 N7 GND 50 TC0.0,
0.0
SPICE netlist written by Bayes2Gates (c) 2002
Ben Vigoda, MIT Media Lab Written on
28-Jun-2002
Xsoftxor_1 N5 N3 N4 N19 N11 N10 GND Vdd
softxor Xsoftxor_2 N11 N10 N9 N8 N7 N1 GND Vdd
softxor Xsoftxor_3 N2 N16 N15 N14 N9 N8 GND Vdd
softxor
MATLAB Bayes Net Toolbox
Spice Netlist