The%20New%20FPGA%20Architecture%20by%20Applying%20The%20CS-Box%20Structure

1
The New FPGA Architecture by Applying The CS-Box
Structure

• Zhou Lin, Catherine
• October 13, 2003

2
Outline

• Introduction to the Xilinx FPGA architecture
• Introduction to the CS-box structure
• Preliminaries
• The connection way of pad pins and wire segments.
• The connection way of logic block pins and wire
  segments.

3
Outline

• Experimental results
• Channel width
• Routing area
• Future work

4
Introduction to The Xilinx FPGA Architecture
5
Introduction to The CS-Box Structure

• Based on the Xilinx FPGA architecture.
• Combines the connection box and the switch box to
  form the connection-switch box (CS-box).

L
L
CS
L
L
6
Introduction to The CS-Box Structure (cont)

• Two types of switches in the CS-box
• Those connecting one wire segment to another.
• They are set in the same way as in the switch box
  in the Xilinx FPGA.
• Those connecting one pin to one wire segment or
  vice versa.
• The way to set them is the main topic in our
  research.

7
Introduction to The CS-Box Structure (cont)

• Two types of CS-boxes
• Containing the switches that connect pad pins to
  wire segments or vice versa.
• Containing the switches that connect logic block
  pins to wire segments or vice versa.

8
Introduction to The CS-Box Structure (cont)

• Preliminaries
• W Channel width. The number of wire segments in
  one channel.
• Fc_pad The number of wire segments each pad pin
  can be connected to.
• Fc_input The number of wire segments each input
  logic pin can be connected to.
• Fc_output The number of wire segments each
  output logic pin can be connected to.
• P The number of non-global pins on each logic
  block or pad.

9
The Connection Way of Pad Pins and Wire Segments

• Fc_pad W
• for i1 to Fc_pad
• if i is even
• Set on the switch connecting the pin to the
  ith track in the x-directed channel.
• else
• Set on the switch connecting the pin to
  the ith track in the y-directed channel.
• endfor

1
L
2
0
Pad
L
10
The Connection Way of Logic Block Pins and Wire
Segments
2

• if W mod P 0
• flag 0
• else
• m W / P
• flag 1
• for i1 to P
• Connect the pin to the tracks with the
  number ki, where k1, 2, , m
• if flag1
• Connect the pin to the track with the
  number (m1)i-W
• endfor

CS
2
2
L
i2
W 3 P 2 ? m 1 flag 1 i 2
11
Experimental Results
Xilinx CS Routing Area
No Buffer Sharing Buffer Sharing
Circuit Name Channel Width Total Circuit per CLB Total Circuit per CLB
alu4 11 12 5.33045e06 5825230 3331.53 3640.77 3.60349e06 3962720 2252.18 2476.7
apex2 11 13 6.43963e06 7039080 3326.25 3635.89 4.35160e06 4786820 2247.73 2472.53
apex4 14 15 5.49633e06 5709500 4240.99 4405.48 3.68954e06 3862570 2846.87 2980.38
b9 4 4 160655 159813 1327.73 1320.77 112001 112861 925.631 932.736
bigkey 7 7 6.26076e06 8650580 2147.04 2966.59 4.25262e06 5858330 1458.37 2009.03
des 7 8 9.63926e06 8598840 2428.64 2166.5 6.52320e06 5913140 1643.54 1489.83
diffeq 8 10 3.71940e06 4531920 2445.37 2979.57 2.52166e06 3072640 1657.90 2020.15
12
Experimental Results (cont)
dsip 6 8 5.42644e06 6327100 1860.92 2169.79 3.70137e06 4352770 1269.33 1492.72
e64 8 9 722875 794783 2501.30 2750.12 493111 546893 1706.27 1892.36
ex5p 14 15 4.62635e06 4804610 4248.25 4411.95 3.1068306 3251530 2852.92 2985.8
misex3 11 12 4.81514e06 5261320 3334.58 3643.57 3.25587e06 3579810 2254.76 2479.1
my_adder 4 4 67195.5 66254.9 1371.34 1352.14 47389.6 47294.2 967.134 965.189
s1423 5 6 357693 441476 1589.75 1962.11 250050 307649 1111.33 1367.33
tseng 7 10 2.35760e06 3253890 2164.92 2987.96 1.60510e06 2207810 1473.92 2027.37
unreg 4 5 67195.5 77096 1371.34 1573.39 47389.6 54754.1 967.134 1117.43
Total 121 137 55486974 61541492.9 37689.95 41966.6 37561181.2 41917591.3 26635.019 28708.655
Incease 13.22 10.91 11.35 11.60 7.79
13
Future

• Do more experiments
• Set Fc_pad, Fc_input and Fc_output equal to W /
  2.
• Apply different switch box structures into the
  FPGA with CS-boxes.