Engineering of Computer-Based Systems

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Engineering of Computer-Based Systems

• Dr. Perry Alexander
• Associate Professor
• alex_at_ittc.ukans.edu
• http//www.ittc.ukans.edu/alex

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Applied Formal Methods
Applied Formal Methods Using Modeling to Develop
Reliable Systems
A Problem to solve, but how?
First, define the problem...
Mathematics defines precisely
?xTP(x) /\ Q(x) /\ R(x) ...
then, design the solution,...
Mathematical Modeling predicts behaviors
?xTP(x)gt?zTQ(x,z) ...
build all the pieces...
P1(x)C1Q1(x,z), P2(x)C2Q2(x,z) ...
Mathematics defines the pieces
and assemble the system...
Mathematics defines correctness
Ip(x)gtIc(x) /\ Oc(x,z)gtOp(x,z)
A Great Computer-Based System
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Modeling Projects

• Network modeling, simulation and verification
• Active Network performance simulation (DARPA)
• Network security and information assurance
  (DARPA)
• Active Network functional correctness (DARPA)
• ASIC modeling and Verification
• Pulse Interval Processor (TRW, AFRL)
• Automated verification obligation generation and
  verification (TRW, AFRL)
• Simulation protocol modeling and verification
• Time Warp distributed simulation verification
  (AFRL)

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Systems Level Design
Systems Level Design Integrating information from
multiple domains into design decision making
P10uW5uW...
Architecture x of CPU is begin x lt fir(y)
wait for xevent end x
X lt F(y) after 5us
Function
Power
Timing
Packaging
Cost
Reliability
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Systems Level Design Projects

• Rosetta language design and tool support
• Systems level modeling language (AverStar, VHDL
  International, AFRL, DARPA, NASA)
• Automated Test Vector Generation (TRW, AFRL)
• Mechanical system redesign demonstration (AFRL)
• Bluetooth demonstration project ongoing (Texas
  Instruments, AverStar)
• Language Standardization to begin next year
• http//www.sldl.org
• VSPEC and VHDL modeling and verification
• Pulse Interval Processor modeling and
  verification (TRW, AFRL)
• Common Signal Processor modeling (TRW, AFRL)

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Architecture and Component Reuse
IP Reuse Reuse of existing software and hardware
components
Component
Component
Input
Output

• Define components and their
• interconnections in an architecture
• Verify the high level architecture
• Find component instances
• Use formal methods to match
• components
• Use formal methods to adapt
• components
• Component reuse with confidence!

Component
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Component Reuse and Retrieval

• Component reuse system
• Retrieval and reuse of VSPEC annotated VHDL
  designs (DARPA)
• Retrieval and reuse of Rosetta annotated system
  components (EDAptive Computing, DARPA)
• Legacy component and replacement
• Retrieval and reuse of components based on match
  with existing legacy systems (EDAptive Computing,
  ONR)

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Other Activities

• Commercialization efforts
• Rosetta Accellera, Texas Instruments, Averstar
  and many others
• Component Retrieval and Reuse EDAptive
  Computing, TRW and others
• Vice Chair, IEEE Engineering of Computer-Based
  Systems Engineering TC
• Member, IEEE Design Automation Standards
  Committee
• Chair, Accellera SLDL Language Subcommittee
• Member, DARPA 21st Century Engineering Consortium
  on Formal Methods Education