Logic Families

1
Logic Families

• ECE-331, Digital Design
• Dr. Ron Hayne
• Electrical and Computer Engineering

2
Logic Implementation

• Physical Phenomena With Two States Can Be Used to
  Implement Switching Algebra
• Most Common
• Voltage
• 0V gt logic 0
• Positive voltage gt logic 1
• Current
• flowing gt logic 1

3
Logic Families

• Based on Underlying Semiconductor Technology
• Transistor-Transistor Logic TTL
• Bipolar junction transistors, BJT
• Metal Oxide Semiconductors MOS
• Field effect transistors, FET

4
MOS Logic Families

• MOSFET
• NMOS n-channel
• Enhancement Mode
• Depletion Mode
• PMOS p-channel
• Enhancement Mode
• Depletion Mode

5
MOSFET

• Four Terminal Device, 3 active
• Source
• Drain
• Gate control terminal
• Small change in source-gate voltage causes large
  change in resistivity between source and drain
• Body non-active terminal
• Typically connected to low (NMOS) or high (PMOS)
  voltage

6
MOSFET

• (Almost) Linear Voltage Amplifier
• Can Be Operated As a Switch to Implement and
  Change Logic Values
• Low Power Consumption Since Operated by Voltage
  vice Current
• Power dissipated in charging/discharging various
  device capacitances through unavoidable
  resistances

7
MOSFET Symbols

• Enhancement NMOS
• Multiple symbols
• Positive VGS reduces resistivity from SD
• Depletion NMOS
• Multiple symbols

8
MOSFETs as Switches
9
Static NMOS

• Totem-Pole Output
• Does not need to be refreshed static
• PMOS Acts as Constant Current Source for Active
  Pull-Up
• Faster rise-times

10
Dynamic NMOS

• Output 1 Unless Discharged
• f1 Charges Output
• f2 Conditionally Discharges Output

11
Static CMOS

• Complementary MOS 2-input NAND

12
CMOS NAND Gate
A B Q1 Q2 Q3 Q4 Z
L L on on off off H
L H
H L
H H
A B Q1 Q2 Q3 Q4 Z
L L
L H
H L
H H
A B Q1 Q2 Q3 Q4 Z
L L on on off off
L H
H L
H H
13
CMOS NAND Gate
A B Q1 Q2 Q3 Q4 Z
L L on on off off H
L H on off off on H
H L
H H
A B Q1 Q2 Q3 Q4 Z
L L on on off off H
L H
H L
H H
A B Q1 Q2 Q3 Q4 Z
L L on on off off H
L H on off off on
H L
H H
14
CMOS NAND Gate
A B Q1 Q2 Q3 Q4 Z
L L on on off off H
L H on off off on H
H L off on on off H
H H
A B Q1 Q2 Q3 Q4 Z
L L on on off off H
L H on off off on H
H L
H H
A B Q1 Q2 Q3 Q4 Z
L L on on off off H
L H on off off on H
H L off on on off
H H
15
CMOS NAND Gate
A B Q1 Q2 Q3 Q4 Z
L L on on off off H
L H on off off on H
H L off on on off H
H H off off on on L
A B Q1 Q2 Q3 Q4 Z
L L on on off off H
L H on off off on H
H L off on on off H
H H
A B Q1 Q2 Q3 Q4 Z
L L on on off off H
L H on off off on H
H L off on on off H
H H off off on on
16
Bipolar Logic Families

• Bipolar Junction Transistor
• Three Active Terminals
• Collector
• Base Control Terminal
• Small change in Ibe causes large change in Ice
• Emitter

17
Bipolar Junction Transistor

• Nonlinear Current Amplifier
• Can Be Operated As a Switch to Implement and
  Change Logic Values
• Relatively High Power Consumption Since Operated
  by Current Flow vice Voltage
• Power dissipated in bulk material due to (small)
  base current and (large) collector current

18
BJT Types

• NPN
• Positive current flowing from base to emitter
  controls current flowing from collector to
  emitter
• PNP
• Negative base current controls Ice

collector
base
emitter
19
TTL NAND Gate
20
TTL NAND Gate
H
L
L
21
TTL NAND Gate
on
H
L
off
on
off
H
22
TTL NAND Gate
on
H
H
off
on
off
L
23
TTL NAND Gate
L
H
H
24
Schottky TTL

• High speed variant of TTL
• Schottky transistors which have faster switching
  speed
• Schottky-barrier diode connected from base to
  collector to prevent transistor from going into
  saturation

25
Merged Transistor Logic

• Minimal TTL Implementation to Reduce Number of
  Passive, Power Dissipating Components
• Integrated Injection Logic I2L
• Multiple collector NPN bipolar transistors
• Can be wire-ord to create all logic functions

26
Emitter-Coupled Logic

• Current steering rather than saturating
  transistors to represent logic 0/1
• Extremely high-speed

27
BiCMOS

• MOSFETs on input to provide high input impedance
• BJTs on output to provide high output current
  switching and good load driving capability

28
Noise Margin

• Difference Between the Worst Case Output Voltage
  of One Stage and Worst Case Input Voltage of Next
  Stage
• Greater the Difference, the More Unwanted Signal
  That Can Be Added Without Causing Incorrect Gate
  Operation

29
Noise Margin

• NMhigh VOHmin - VIHmin
• NMlow VILmax - VOLmax

Sample Data Sheet
30
Speed

• Rise Time
• Time from 10 to 90 of signal
• Fall Time
• Time from 90 to 10 of signal
• Propagation Delay
• Time from input signal reaching 50 point to
  output signal reaching 50 point

31
Propagation Delay
Sample Data Sheet
32
Power Dissipation

• Static
• I2R losses due to passive components
• Dynamic
• I2R losses due to charging and discharging
  capacitances through resistances

33
Fan-In

• Number of input signals to a gate
• Not an electrical property

34
Fan-Out

• A Measure of the Ability of the Output of One
  Gate to Drive the Input of Subsequent Gates
• Usually Specified As Standard Loads Within a
  Single Family
• May Have to Compute Based on Current Drive
  Requirements When Mixing Families

35
Fan-Out
Sample Data Sheet
36
Wired-Logic

• Open collector outputs connected together to a
  common pull-up resistor
• Any collector can pull the signal line low
• Logically an AND gate

37
Tri-State Logic

• Both output transistors of totem-pole output are
  turned off
• Usually used to bus multiple signals on the same
  wire
• Gates not enabled present high-Z to bus and
  therefore do not interfere with other gates
  putting signals on the bus

38
End of Lecture

• MOS
• TTL
• Schottky
• ECL

• Noise Margin
• Speed
• Power
• Fan Out