FSM Structures

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FSM Structures

• Mealy, Moore and Combined Mealy/Moore outputs
• Figure 8.3

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Bad FSM Model

• State Diagram

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Problems of FSM1 BAD

• no reset, no next state value defined for the
  unused state.
• 2bits FFs 3 states used, one unused state.
• Read and Write output assignment infer extra two
  FFs.
• To avoid extra FFs, use separate combinational
  process.
• variable initialization
• Ignored by the synthesis tools.

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FSM1_GOOD
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Synthesized Circuit
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FSM 2

• State Diagram

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• Output Y
• Assigned under clockevent statement.
• Extra FFs are inferred.

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Good Model 1 (1 sequential process, 1 combination
process, selected signal assignment for Y)
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Sequential process Combinational process

• Sequential process
• Description with respect to the edge point
• Input sampled just before the edge
• Output
• Combinational process

input
output
input
output
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FSM 2_GOOD2

• Combined current state and next state logic
• Separate output logic

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Separate output logic
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Synthesized Circuit
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FSM 2_GOOD3

• Combined next state and output logic
• Separate current state logic

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VHDL Code
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FSM 2_GOOD4

• Combined current state, next state and output
  logic

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VHDL Code
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Car Speed Controller FSM

• State Diagram

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Input primary branch directives
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State value primary branch directives
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Angular Position FSM using Gray and Johnson state
encoding

• State Diagram

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• Input
• Physical Position asynchronous input(loaded when
  reset 1)
• MOVE CW 45 clock wise move
• MOVE CCW 45 counter clock wise move
• Two ways of representing state encoding
• Use a signal of an enumerated type for which a
  single synthesis specific attribute is applied.
  Attribute name is specific to the synthesis tool,
  not portable, needs to be changed.

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VHDL Code
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• 2. Use constants to represent the individual
  state values. It is directly portable to other
  synthesis tools.

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Angular position FSM
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Black Jack Game Machine

• Blackjack Game
• Blackjack is the most popular of the card games
  played at the tables in casinos. It is played
  with a standard deck of 52 cards. The four suits
  spades, hearts, diamonds and clubs have no
  significance and are ignored. The Jack, Queen and
  King all have a value of 10. The ace is the most
  powerful card having a value of 1 or 11 depending
  upon what the player chooses.
• Blackjack is also known as pontoon or 21
  because 21 is the highest rated total card value
  a player can hold. Blackjack is the name given to
  the strongest hand consisting of an ace and a 10
  valued card.
• The object of the game is to beat the dealer. The
  dealer has no object other than to follow the
  rules of the casino, which is to stand(hold) on
  hands of 17 or more, and to draw another card on
  hands of 16 or less.
• A player looses if his or her total card value is
  less than the dealers total, or, he or she has
  over 21 and so has bust. If a player wants to
  improve his hand he can ask the dealer for
  another card. This is called drawing or hitting.
  If satisfied with the total card value he can
  stand(hold).

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VHDL package defining four enumerated state
encoding data types
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FSM with selectable state encoding Blackjack
game machine
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FSMs with a Mealy or Moore output

• State Diagram for FSMs with a Mealy and Moore
  output

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FSM modeled with NewColor as a Mealy type output
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FSM modeled with NewColor as a Moore type output
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FSM modeled with a Mealy and a Moore Output
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• Moore Output
• Dependent only on the current state, early output.

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FSM with sequential next state logic

• Extra FF in the next state logic.
• State Diagram
• BeenlnState3B (extra FF)

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FSM with sequential next state logic
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• Inferred FSM Structure with an additional FF in
  the next state logic

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FSM with sequential output logic

• FSM with sequential output logic
• State machine with an embedded counter
• Counter parts of the state machines output
  logic.
• State diagram implying sequential output logic

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State diagram implying sequential output logic
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FSM with sequential output logic
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Tried to use a synchronized value ?? ??
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Inferred FSM Structure with embedded counter
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FSM with sequential next state and output logic -
Blackjack

• Figure 8.12 State Diagram
• VHDL coded with one single process statement.

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VHDL Code
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Interactive State Machine

1. Unidirectional

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Interactive State Machine

• 2. Bidirectional

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Unidirectional interactive FSMs

• Three different ways of controlling data path
  with unidirectional interactive FSMs

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Data Path

• Data Path
• Accepts three or four 4-bits values on the input.
• Processes them, to provide sequences of either
  two or three, 9-bits values on the output.
• Input data A, B, C, D
• Output data Y1, Y2, Y3, (Y4)
• When ThreeOnly 0
• Y1 A.B A.C
• Y2 A.D B.C
• Y3 B.D C.D
• When ThreeOnly 1
• Y1 A.B A.C
• Y4 B.C
• Data Path controlled from Control Path 1, 2, 3

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Control Path 1

• Control Path
• FSM master
• send Start FSM1, Start FSM2, Start FSM3
• FSM 1
• Dedicated to provide four enable signals used to
  clock the serial input data into the appropriate
  holding register.
• FSM 2
• Send select signals which of the two held inputs
  to multiply together.
• Provide enable signals used to clock the
  multiplied result into the appropriate state
  register.
• FSM 3
• Simply provide the select lines used to select
  which result to output.

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• Control Signals in control path 1

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• Master FSM state diagram and FSM1, FSM2, FSM3
  state diagram

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Control Path 2

• Three state diagram

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• Control Path state diagram

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1. Data path(VHDL Code)
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2. Control Path 1(VHDL Code)
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3. Control Path 2 (VHDL Code)
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4. Control Path 3 (VHDL Code)
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Two Interactive FSM Controlling rotors

• Two Interactive FSM Controlling rotors
• To control two mechanical interlocking rotors,
  which rotate in 90 increments in a clockwise or
  counter clockwise.

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• Two Interactive FSM Controlling rotors
• FSM1(FSM2) controls the rotor R1(R2)
• Four states(Ang0, Ang90, Ang180, Ang270)
• Inputs CW-R1, CCW-R1, CW-R2, CCW-R2
• Two rotors should not be in the same position
• Primary drive, Secondary drive
• Cannot be in or moved to some where if it is not
  occupied by the primary drive
• R1_R2b 1 R1 is drive
• R1_R2b 0 R2 is drive

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VHDL Code
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