One flew over the SystemC nest

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One flew over the SystemC nest

• Jan Schmidt

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Overview

• Principles of operationexplains how the SystemC
  library works, aims at understanding of
  advantages, limitations and innovative use
• verification and synthesis with SystemC
• levels of abstraction
• HW/SW co-verification with SystemC
• potential for future applications

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Classes for simple circuit simulation in C
Class signal
eval()
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Objects simulating a circuit
// objects decls main () start_simulation()
ALU1
adder
A
Q
B
Y
module
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SystemC runtime phases
elaboration
constructors running
static DRC
final static DRC
main() running
simulation
dynamic DRC
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Instead of eval()

• C member functions
• representing processes
• each explicitly registered for a module
• each having a sensitivity list
• Processes
• SC_METHOD started by an event in sensitivity
  list, does not release control, does not require
  separate stack, synthesizable
• SC_THREAD can be suspended and wait for
  enumerated events (dynamic sensitivity list),
  requires separate stack, coroutine execution
  (non-preemptive), non-synthesizable
• SC_CTHREAD as above, sensitive to clock only

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Base SystemC terms and SystemC 2 generalizations
SystemC 1
SystemC 2
module
module
port
port
signal
channel interface
signal change
event
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Channel/port linking mechanism
data class T
parametri-zation
access methods declaration but no implementation
interface class ifltTgt
inheritance
channel
port
runtime link
access methods implementation
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Sensitivity to events ports
data class T
sensitivity list (of events)
parametri-zation
default event
interface class ifltTgt
process
Is sensitive to
inheritance
channel
port
elaboration-time link
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C syntax pitfalls
Confuse the enemy. It does not matter that you
confuse your own troops Czechoslovak Peoples
Army tradition
MyObject obj(a,b,c)
parameters to a constructor
Generic List specialized to hold int
Listltintgt
Object used as a function
obj(p,q)
obj.operator()(p,q)
Overloaded shift operator
obj ltlt p ltlt q
obj.operatorltlt (p)obj.operatorltlt (q)
SystemC macro obliterating class header
SC_MODULE(dff)
class dff public module
SystemC macro obliterating base class
initialization
dff() module(dff)
SC_CTOR(dff)
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DFF
dff.h
dff.cc
include systemc.h SC_MODULE(dff)
sc_inltboolgt din sc_inltboolgt
clock sc_outltboolgt dout void doit()
SC_CTOR(dff) SC_METHOD (doit) sensitive_pos
ltlt clock
include dff.h void dffdoit() dout
din
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Applications simulation

• evaluate and update phase (delta time)
• clock generators and waweform definition
• trace and observation support
• sc_logic 0, 1, X, Z
• sc_fixed fixed point data type, DSP
• sc_intltngt, sc_uintltngt
• all C data types and classes
• all C constructs, inheritance, virtual
  functions, access control, templates

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Applications RTL synthesis

• Limited subset of SystemC features
• bool for simple signals
• sc_int, sc_uint
• sc_logic when necessary
• integer C types for loop control
• no inheritrance and operator overloading outside
  of SystemC own usage
• no pointers, no virtual functions, no global
  variables, no exception handling
• no obviously non-synthesizable features, like
  files
• as close semantically to structural VHDL as
  possible?

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Methodology

• stepwise process refinement
• start with C algorithm specification
• manually replace behavioral code with RTL code
• verify after each step
• stepwise communication refinement
• start with master-slave RPC channel communication
• construct adapters that implement RPC with real
  communication medium, verify
• absorb adapters into communicating processes
• supported by specialized library
• other methodolgies expected

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Co-design and co-verification
Abstract levelUniTimed Functional (UTF)
refinement
SW
HW
Bus Cycle Accurate (BCA)
GenericRTOS
RPC
refinement
RTOS
RTL
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Bus Functional Model (BFM)
untimed
C/C
HW
BFM
cycle-accurate
Instruction set simulator
HW
BFM
assembly
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Opportunities for subversion and misuse

• current SystemC targeting and use
• modelling and verification (we will die of
  verification)
• RTL synthesis
• information accessible by extension or
  modification of the SystemC library
• module / port / channel structure
• executable code of the processes
• operations on data types can be overloaded
• to go further
• C parser (Roskinds grammar and others)
• existing front end (gcc)

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Silly ideas (instead of conclusion)

• symbolic simulation
• derivation of BFMs from high-level processor
  decription
• model checking
• making true OO hardware description synthesizable
• models of evolving hardware