Lecture 2 Low Power Bus Encoding Techniques

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Lecture 2 Low Power Bus Encoding Techniques

• Instructor Jun Yang

2
Overall Architecture
Off-chip Cache/Memory
Data Bus
CPU
On-chip Cache
Address Bus
3
Motivation

• Capacitance of external buses is high.
• Capacitance of the external bus is order of
  magnitude higher than internal bus.
• Power consumption can be reduced by minimizing
  switching activity of external buses.

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Address Bus Encoding

• Address bus switching activity can be
  substantially reduced.
• Memory reference locality.
• Gray Code
• C. L. Su, C. Y. Tsui, and A. M. Despain, Saving
  Power in The Control Path of Embedded
  Processors, IEEE Design and Test of Computers,
  pages 24--30, Vol. 11, 1994.
• T0
• L. Benini, G. De Micheli, E. Macii, D. Sciuto, C.
  Silvano, Asymptotic Zero-Transition Activity
  Encoding for Address Buses in Low-Power
  Microprocessor-Based Systems, IEEE 7th Great
  Lakes Symposium on VLSI, Urbana, IL, pp. 77-82,
  Mar. 1997.
• T0-C
• Y. Aghaghiri, F. Fallah, and M. Pedram,
  Irredundant Address Bus Encoding for Low
  Power,' ACM/IEEE International Symposium on Low
  Power Electronics and Design, pages 182--187,
  August 2001.

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Data Bus Encoding

• Less regular. For long time, assumed the value as
  random values.
• Bus-invert
• M. R. Stan and W. P. Burleson, Bus-invert
  coding for low-power I/O, IEEE Transactions on
  Very Large Scale Integration (VLSI) Systems,
  pages 49--58, Vol. 3, 1995.
• Adaptive
• L. Benini, A. Macii, E. Macii, M. Poncino, and R.
  Scarsi, Synthesis of Low-Overhead Interfaces for
  Power-Efficient Communication Over Wide Buses,
  ACM Design Automation Conference, pages 128--133,
  1999.

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Frequent Value Data Bus Encoding
FV Encoder/ Decoder
Off-chip Cache/Memory
Data Bus
CPU
On-chip Cache
Address Bus
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Basic Scheme
0xff
0x00
0xff
0x00
0x08
0x08
0x08
0x00
0x00
0xff
0xff

• The encoder and decoder store the last n (n is
  the bus width) values appeared on the bus.
• If a new value v is the same as the ith value in
  encoder, send the unary form of the index i onto
  the bus 00100 (1 is the ith bit).
• If it is not stored in the encoder, send the
  original binary v onto the bus.

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Enhanced Scheme
But

• Switching of nonfrequent-frequent value pair may
  be high.
• Switching of frequent-frequent value pair is 2.

0x00
0xff
0xff
0xff
0x00
0x00
Correlator
Decorrelator
Correlator switches only wires whose input is 1.
What is the problem with this improvement?
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Maintaining the n most recent values

• Suppose n 8
• For the first 8 distinct values, allocate each
  one of them an empty entry in the encoder
• For the 9th value, if it is still different from
  all of the previous 8 values, select a victim
  from the 8 and replace it with the 9th value
  replacement policy!
• Use LRU replacement policy. In this example, pick
  the 1st value that came into the encoder.

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Implementing LRU

• Reference bit is shifted right at regular
  intervals to form the timestamp.
• Timestamps (and reference bits) are used to
  implement LRU replacement policy.

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Reducing Encoder Overhead

• Reduce number of entries in the coder, i.e. store
  fewer values.
• Smaller sized coder consumes less energy.
• Use a fixed set of frequent values.
• Remove activities in updating values and the
  timestamps.
• Reduce the number of accesses to the coder.
• Filtering out values with few 1s.
• Will not reduce the performance.

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Project 2

• Measure the power consumption, the delay and the
  area overhead for the encoder and decoder.
• The encoder/decoder can be implemented as CAM
  (Content Addressable Memory).
• Add additional logic to the CAM to implement the
  LRU replacement policy
• Use any tools that you feel comfortable with,
  e.g. VHDL.

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Project 3

• How does the delay in data bus encoding affect
  the overall system performance? (how does it
  increase the program execution time in terms of
  number of cycles?)
• Suggested tool SimpleScalar