Tang Wai Chung, Matthew

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CEG3470
Digital Circuits (Spring 2009)
Lecture 7 MOS Transistor Model
Courtesy slides from DIC 2/e and EE141 notes
from Prof. Jan Rabaey

• Tang Wai Chung, Matthew

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NMOS Transistor Structure

• p-type material doped with acceptor ? holes ()
  as majority carriers
• n-type material doped with doner ? electrons (-)
  as majority carriers
• When S G D 0V, both p-n junctions have 0V
  bias and considered off.

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Threshold Voltage Concept

• With positive gate bias, electrons pulled toward
  the gate
• With large enough bias, enough electrons will be
  pulled to "invert the surface (p ? n type)
• Voltage at which surface inverts magic
  threshold voltage VT

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The Threshold Voltage

• Threshold
• Fermi Potential

2 ?F is approximately 0.6V for p-type
substrates ? is the body factor VT0 is
approximately 0.45V for 0.25 ?m process.
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Transistor with Gate and Drain Bias
cap. per unit area (gate oxide)
electron mobility (m2/(V s))
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Transistor with Gate and Drain Bias
VGS
VDS
ID
-

V(x)
Doing Integration, we have
where
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Transistor in Saturation
0 lt VGS VT lt VDS
VGS
VDS gt VGS VT
ID
-

VGS VT
Replacing VDS with VGS VT
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Saturation

• For (VGS VT) lt VDS, the effective drain voltage
  and current saturate
• Of course, real drain current isnt totally
  independent of VDS

approx. for channel-length modulation
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Modes of Operation
Cutoff
VGS VT lt 0
ID 0
Linear (Resistive)
VGS VT gt VDS
Saturation
0 lt VGS VT lt VDS
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Current-Voltage Relations Old Transistor
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Current-Voltage Relations The Deep Sub-Micron
Transistor
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Velocity Saturation

• Velocity saturates due to carrier scattering
  effects

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Velocity Saturation (Cont)
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ID versus VGS
Long Channel (L 2.5?m)
Short Channel (L 0.25?m)
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Including Velocity Saturation
Approximate velocity
continuity requires that
Integrating to find the current again
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Regions of Operation
Long Channel (L 2.5?m)
Short Channel (L 0.25?m)
W/L 1.5
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Models

• Exact behaviour of transistor in velocity sat.
  somewhat challenging
• If you want to analyze easily, use MODELS.
• There are many different modelsv-sat, alpha,
  unified VT, etc.
• Simple model for manual analysis desirable
• Assume velocity perfectly linear until ?sat
• Assume VDSAT constant

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Simplified Velocity Saturation

• Assume velocity perfectly linear until hit ?sat

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Simplified Velocity Saturation (Cont)

• Assume VDSAT ?cL when (VGS VT) gt ?cL

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A Unified Model for Manual Analysis
Define VGT VGS VT for VGT 0 ID 0 for VGT
0
with
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Simplified Model

• Define VGT VGS VT, VD,SAT ?cL

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Simple Model vs SPICE
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One Last Simplification

• If device always operates in velocity sat.
• V_T model
• Good for first cut, simple analysis

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Transistor Model for Manual Analysis
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A PMOS Transistor
All variables negative Work with absolute values
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MOS Capacitance
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Gate Capacitance
CO Cox xd

• Capacitance (per area) from gate across the oxide
  is W L Cox, where Cox ?ox/tox
• The overlap capacitance CGSO CGDO COW

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Transistor In Cutoff

• When the transistor is off, no carriers in
  channel to from the other side of the capacitor
• Substrate acts as the other capacitor terminal
• CGCB CGC WLCox

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Transistor In Cutoff (2)

• As VGS increases andVGSltVT, a depletion
  region is formed and act as a gate dielectric ?
  CGCB started to drop from W L Cox
• It finally becomes 0 when VGS VT

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Transistor In Linear Region
1/2
1/2

• Channel is formed and acts as the other terminal
• GGCB drops to zero (shielded by channel)
• Model by splitting oxide cap equally between
  source and drain
• Changing either voltage changes the channel
  charge and hence the capacitance

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Transistor in Saturation Region
gt1/2
lt 1/2
pinch-off

• CGCD drops as VDS increases ? drop to 0 when the
  channel pinches off.
• CGCS gradually rises from WLCox/2 to (2/3)WLCox

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Gate Capacitance
Cgate vs. VGS (with VDS 0)
Cgate vs. operating region
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Average Distribution of Channel Capacitance
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Gate Fringe Capacitance

• COV not just from metallurgic overlap get
  fringing fields too
• Typical value 0.2 fFW (in ?m)/edge

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Diffusion Capacitance

• Bottom
• Area cap.
• Cbottom Cj Ls W
• Sidewalls
• Perimeter cap.
• Csw Cjsw (2Ls W)

Cdiff CjLsW Cjsw(2Ls W)
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Capacitance Model Summary

• Gate-Channel Capacitance
• CGC ¼ 0
• CGC CoxWLeff50 G to S, 50 G to D
• CGC (2/3)CoxWLeff100 G to S
• Gate Overlap Capacitance
• GGSO CGDO CO W
• Junction/Diffusion Capacitance
• Cdiff Cj Ls W Cjsw(2Ls W)

(VGSltVT)
(Linear)
(Saturation)
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MOS Capacitances
G
CGS CGCS CGSO
CGD CGCD CGDO
S
D
CDB Cdiff
CSB Cdiff
CGB CGCB
B
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Example

• Consider an NMOS transistor with the following
  parameters Cox 5.7 fF/?m2, L 0.24 ?m, W
  0.36 ?m, LD Ls 0.625 ?m, CO 310-3 F/m,
  Cj0 210-3 F/m2, and Cjsw0 2.7510-10 F/m.
  Determine the zero-bias value of all relevant
  capacitances

CGC WLCox 0.36? 0.24? 5.7 0.492 fF CG
0.492 0.36?(3 10-10) 0.700 fF Cdiff
Cj0LDW Cjsw0(2LD W) 210-3 x 0.625? 0.36?
2.75 10-10 (2 0.625? 0.36?) 0.450
0.442 0.892 fF
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Capacitances in 0.25?m CMOS Process