An Efficient Wakeup Schedule during Power Mode Transition Considering Spurious Glitches Phenomenon

1
An Efficient Wake-up Schedule during Power Mode
Transition Considering Spurious Glitches
Phenomenon

• Yu-Ting Chen
• Da-Cheng Juan
• Ming-Chao Lee
• Shih-Chieh Chang
• Department of CS, National Tsing Hua University,
  Taiwan

2
Outline

• Introduction
• Surge current analysis
• Wake-up schedules for wake-up time minimization
• Experimental Results Conclusions

3
Outline

• Introduction
• Surge current analysis
• Wake-up schedules for wake-up time minimization
• Experimental Results Conclusions

4
Power Gating Technique

• In deep sub-micron, leakage is significant on
  total power consumption.
• Power gating is one of the most effective ways to
  reduce leakage power.

VDD
Low VTH devices
Active Mode
Sleep Mode
Turn-On
Turn-Off
GND
5
DSTN Structure
VDD
Cluster 1
Cluster 2
Cluster 3
VGND
High VTH sleep transistor
GND

• Distributed Sleep Transistor Network (DSTN)
  structure is adopted by many industrial designs.
• Sleep transistors are connected by the virtual
  ground line (VGND).

6
Sleep Mode
VDD
Cluster 1
Cluster 2
Cluster 3
VGND
GND

• During sleep, internal devices and the virtual
  ground are charged.
• With enough time, all capacitances will be
  charged to the level close to VDD.

7
Power Mode Transition
VDD
Cluster 1
Cluster 2
Cluster 3
VGND
Turn-off sleep transistors
GND
Surge current

• When sleep transistors are turned on, a sudden
  discharging current occurs, called surge current.
• Excessive surge current affects the reliability
  of a circuit.
• Ldi/dt
• IR drops
• Electromigration (EM)

8
Surge Current Constraint

• Constraining the surge current is vital for power
  gating design.
• The current flowing through sleep transistors is
  proportional to the total size of the turned-on
  sleep transistors.
• The number and the timing to turn on sleep
  transistors should be restricted.

9
Wake-up Schedules

• Wake-up schedule
• The turn-on sequence of sleep transistors
• Major challenge to constraint the surge current

VDD
VGND
GND
ST1 gt ST2 gt ST3
10
Previous Works

• Turn on one sleep transistor per clock cycle,
  from the smallest size to the largest size.
• S. Kim, and et al, Understanding and Minimizing
  Ground Bounce during Mode Transition of Power
  Gating Structures, Proc. of the ISLPED, Aug,
  2003.

VDD
VGND
GND
Cycle 1
Cycle 2
Cycle 3
11
Observation 1 Surge Current vs. Wake-up Time
One-by-One turns on sleep transistors one by
one in a one-nanosecond time interval
All-On turns on all sleep transistors
simultaneously
8.4ns
4.8ns
I
V
t
t
12
The Dilemma Scenario
I
V
t
t

• Wake-up schedule design
• Efficient wake-up time , surge current
• Reliable wake-up time , surge current
• Modeling the scenario as a scheduling problem
  under a surge current constraint.

13
Observation 2 Spurious Glitches
VDD
V
VA
VVGND
VA
VGND
VVGND
GND
t

• Virtual ground needs sufficient time to be
  stabilized to ground
• Several spurious glitches occur on internal node

14
Outline

• Introduction
• Surge current analysis
• Wake-up schedules for wake-up time minimization
• Experimental results Conclusions

15
Surge current vs. Wake-up Time
I
Surge current constraint
t

• Surge current determines the speed to discharge
  energy.
• A short wake-up time can be achieved with a large
  surge current
• Design the wake-up schedule to control the surge
  current close to but not exceed the constraint.
• An accurate upper bound of surge current
  estimation.

16
DSTN Under Power Mode Transition
VDD
Cluster 1
Cluster 3
Cluster 2
VGND
I(ST2)
I(ST3)
I(ST1)
GND

• V(STi) the voltage across STi
• I(STi) the current flowing through turned-on
  STi
• Surge current SI(STi) for all i

17
Surge Current vs. Virtual Ground

• I(STi) can be expressed as
• Saturation region
• I(STi) kn W(STi) / L (VDD VTH)2 (1
  ?V(STi))
• Linear region
• I(STi) kn W(STi) / L ( (VDD VTH) V(STi)
  V(STi)2 / 2 )
• Given W(STi), I(STi) only depends on V(STi).

VDD
Low VTH devices
I(STi)
STi
GND
18
Characteristics of V(STi)s
V
VDD
STi
V(STi)
GND
t

• V(STi)s are hard to be calculated analytically.
• Time varying
• Spurious glitches
• Empirically, V(STi)s are strictly decreasing in
  DSTN designs.
• Use this to estimate surge current and design the
  wake-up schedule

19
Outline

• Introduction
• Surge current analysis
• Wake-up schedules for wake-up time minimization
• Experimental results Conclusions

20
The Flow of WTM
V
SC_CONSTRAINT 100
Turn on ST1
Wake-up time 90 30 60
surge current 90
surge current 5535 90
Iteration 1
90
30
60
t

• Step 1 Update all V(STi)s by using a SPICE-like
  simulator.
• Step 2 Calculate all I(STi)s according to
  V(STi)s.
• Step 3 Determine which sleep transistors to be
  turned on.
• If all STis are turned on and all V(STi)s are
  within 5 of VDD, the process completes.
• Otherwise, go to Step 1.

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Physical Implementation Issues

• Our model places sleep transistors at both ends
  of a row
• ST1, ST3, ST4, ST2, ST5 does NOT conform to
  their order of physical placement.
• A schedule without conforming to the physical
  placement
• A large area penalty causes the schedule not
  practical

ST1
ST2
ST3
ST4
ST5
22
Physical Implementation Issues (contd)

• Conforming to the physical order
• (1) ST1, ST2, ST3, ST4, ST5 unidirectional
• (2) (ST4), (ST5, ST3), (ST2, ST1)
  bidirectional

ST1
ST2
ST3
ST4
ST5
23
Intelligent Wake-up Time Minimization (IWTM)

• Like WTM, IWTM also uses the properties of surge
  current to develop an efficient schedule.
• IWTM improves WTM on physical implementation
  issues.

24
The Flow of IWTM
The weight of row
ST1
12
ST2
15
ST3
13
ST4
17
ST5
15

• Step 1 Calculate the weights of each row.
• Step 2 Prioritize STi according to the weight
  of each row.
• Step 3 Choose a starting STi under the surge
  current constraint.

25
The Flow of IWTM (contd)
Wake-up Schedule (ST4), (ST5, ST3), (ST2,
ST1)
ST1
ST2
ST3
ST4
ST5

• Step 4 Update V(STi)s and I(STi)s.
• Step 5 Determine how many sleep transistors can
  be turned on. Only STi which has a turned-on
  neighbor can be turned on.
• If all STis are turned on and all V(STi)s are
  within 5 of VDD, the process completes.
• Otherwise, go to Step 4.

26
Outline

• Introduction
• Surge current analysis
• Wake-up schedules for wake-up time minimization
• Experimental results Conclusions

27
Environment Setup

• Environment setup
• TSMC 90nm process
• Update V(STi) and I(STi) every 30ps.
• Use the maximum instantaneous current (MIC) as
  the surge current constraint.
• Insert decoupling capacitances on the virtual
  ground
• Re-implemented the second method of 1 and
  compared that with our WTM and IWTM.
• 1 S. Kim, and et al, Understanding and
  Minimizing Ground Bounce during Mode Transition
  of Power Gating Structures, Proc. of the ISLPED,
  Aug, 2003.

28
Experimental Results

• AES
• 643 times faster in wake up time
• 75.81 less in energy loss

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Conclusions

• Minimize the wake-up time on the DSTN structure
• Our method considers
• surge current estimation
• spurious glitches
• physical implementation
• IWTM can achieve
• 332X wake-up time reduction
• 35.48 energy loss reduction

30

• Thank you
• Q A

31
DSTN Active Mode
VDD
VGND
GND

• The linear system model
• Logic clusters ? current sources
• Sleep transistors each segment of VGND ?
  resistors
• Take decoupling capacitances into account.

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Wake-up Time
VDD
Voltage (v)
1
V(ST3)
VST3
VST1
VST2
VGND
V(ST1)
V(ST2)
ST1
ST3
ST2
0.05
GND
0
T1
T2
Time (ps)

• A circuit is waken up only when
• All sleep transistors are turned-on (T1) and
• all segments of virtual ground are under 5 of
  VDD (T2).
• Wake-up time Max T1, T2

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Problem Formulation

• Inputs
• All sleep transistors sizes
• A surge current constraint
• A wake-up vector
• Decision Variables
• The turn-on timing of each sleep transistor
• Objective
• Minimize the wake-up time
• Subject to
• surge current surge current constraint

34
Previous Works

• S. Kim, and et al, Understanding and Minimizing
  Ground Bounce during Mode Transition of Power
  Gating Structures, Proc. of the ISLPED, Aug,
  2003.
• Turn on all sleep transistors by a weak wake-up
  signal.
• Turn on one sleep transistor per clock cycle,
  from the smallest size to the largest size.

Cycle 1
Cycle 2
Cycle 3
35
The Strictly Decreasing Property
Iturnon(ST1, t30) 90mA
SC_CONSTRAINT 100 mA.
Voltage (v)
1
90
Time (ps)
60
Iturnon(STi) is also strictly decreasing between
30ps to 60ps
From 30ps to 60ps surge current Iturnon(ST1)
lt 90mA lt SC_CONSTRAINT

• V(STi) is strictly decreasing. gt Iturnon(STi) is
  strictly decreasing.
• Surge current SIturnon(STi) for all i
• will not exceed the constraint during the wake-up
  process.

36
Spurious Glitches Phenomenon
Schedule A
Schedule B
logic 1

• Different schedules gt different seriousness of
  spurious glitches
• Two schedules
• Schedule A is Tturnon(ST1) 2, Tturnon(ST2)
  0, Tturnon(ST3) 4
• Schedule B is Tturnon(ST1) 0, Tturnon(ST2)
  2, Tturnon(ST3) 4
• Schedule B is superior than Schedule A.

37
Spurious Glitches Phenomenon (contd)
Schedule A
Schedule B
Tturnon(ST1) 2
Tturnon(ST1) 0
logic 1

• A gate is topologically close to primary inputs
  should be stabilized earlier.
• Avoid the propagation of spurious glitches.
• To make a gate be stablized earlier
• The corresponding V(STi) of this gate should be
  stabilized first.
• V(STi) can be stabilized faster by turning on STi.

38
Implementation Flow
RTL Netlist
Existing tools
Our tools
Synthesis
Gate-level Netlist
Capacitance file
Placement
Wake-up Vector
DEF file
Sleep Transistors Size file
Surge current Constraint file
DSTN Design Generator
Wake-up Schedule file
Design file
IWTM Engine
Footer ST Behavior file
Virtual Ground Behavior file
Wake-up time
NanoSim