Balancing Interconnect and Computation in a Reconfigurable Array

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Balancing Interconnect and Computation in a
Reconfigurable Array
Why you dont really want 100 LUT utilization

• Dr. André DeHon
• BRASS Project
• University of California at Berkeley

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Question

• How much interconnect do I need for my
  computing/programmable array?
• Problem(?) too little interconnect
• ?wont be able to use all the gates/LUTs
• Typical subgoal how much interconnect to use
  (almost) all LUTs?

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Wrong Subgoal

• Observation
• interconnect is dominant area on FPGAs
• more important to use interconnect efficiently
  than to use LUTs efficiently
• Different question/subgoal
• What level of interconnect gives the least
  implementation area for applications?

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LUT Utilization predict Area?
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Outline

• Question how much interconnect?
• Teaser less than 100 LUT utilization
• Model
• Application characteristics
• Compose
• Conclusions

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Model Interconnect Requirements and Richness

• Recursively partition (bisect) design
• Look at I/O from each partition (subtree)

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Regularizing Growth

• How do bisection bandwidths shrink (grow) at
  different levels of bisection hierarchy?
• Basic assumption Geometric
• 1
• 1/?
• 1/?2

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Rents Rule

• Long standing empirical relationship
• IO C?NP
• 0?P ?1.0
• Embodies geometric assumption (C,P)
• Two parameters
• C base of growth
• P capture growth (a 2P)
• Captures notion of locality

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Define Network with Parameters
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Cartoon VLSI Area Model
(Example artificially small for clarity)
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Effects of P on Area
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Application Requirements Benchmark Wide (MCNC)
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Benchmark Parameters
Interconnect requirements vary across
applications.
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Network Fixed Schedule

• Network will have a fixed wiring schedule
• Applications have varying requirements
• To assess impact of mismatch
• map to network schedules
• look at area required

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Mapping Problem

• When design interconnect exceeds network
• have to repartition to meet
• fixed wire schedules of
• target network
• depopulating LUTs as
• necessary
• See paper/poster for
• one approach

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Resources ? Area Model gt Area
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Picking Network Design Point
(8l wire pitch 2500l2 switchpoints linear
population)
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Summary

• Interconnect area dominates
• logic block area
• Interconnect requirements vary
• among designs
• within a single design
• To minimize area
• focus on using dominant resource (interconnect)
• may underuse non-dominant resources (LUTs)