AIDA update

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AIDA update Steve Thomas ASIC Design Group 9
December 2008

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Overview
Digital design Place and route Pin
positioning Analogue matching Threshold
mismatch PORGAMRAYS result Simulation Time-scales
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Digital layout (test version)
Signals for one channel, mostly grouped in pairs
(differential mode to minimise substrate
coupling)
Full layout
Bottom edge, with control register connections
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Threshold mismatch
Vth0 matching for PMOS 15mV/sqrt(WL) Matching is
important for low current mirrors, eg feedback
circuit. Mismatch may be due to other factors,
not included in the models (interface charge, for
example). The correct model is essential for
optimising low current circuits.
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Process monitor results (PORGAMRAYS)
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Subthreshold plot varying Vth0
Vth0 variation causes constant threshold mismatch
over all currents Range of Vth0 is 80mV, in
order to cause factor of 10 difference in leakage
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Subthreshold plot varying Cit
Cit variation causes large threshold mismatch at
low current, but better matching at high current.
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Statistical simulation varying Vth0 Cit
Leakage / threshold plot, equivalent to process
monitor results. Simulation can be extended for
complete analogue channel
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Time-scales
Completion of top-level layout December Final
checking, design review January (deadline
26th) Manufacture Feb - April Testing May
June Second iteration start as soon as test
results are available (beam tests not essential).
Finalisation of second iteration definitely needs
physics test results.