Verilog HDL. ?a

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??-220

• Verilog HDL. ?a ßas???...

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?as??? ??? S?ed?as??
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?? e??a? ? Verilog

• Verilog Hardware Description Language(HDL)
• ??a ?????? ep?p?d?? ???ssa p?? µp??e? ?a
  a?apa?aste? ?a? ?a p??s?µ????e? ??f?a??
  ?????µata.
• Hardware concurrency
• Parallel Activity Flow
• Semantics for Signal Value and Time
• ?a?ade??µata s?ed?as?? µe Verilog HDL
• Intel Pentium, AMD K5, K6, Athlon, ARM7, etc
• Thousands of ASIC designs using Verilog HDL
• Other HDL SystemC, VHDL

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??apa??stas? ??f?a??? S?st?µ?t??

• Verilog HDL ???s?µ?p??e?ta? ??a ?a ft???e?? t?
  µ??t??? e??? s?st?µat??.
• ?????
• requirements specification
• documentation
• testing using simulation
• formal verification
• synthesis
• St????
• most reliable design process, with minimum cost
  and time
• avoid design errors!

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S?µß?se?? st?? ???ssa Verilog

• ? Verilog e??a? case sensitive.
• ???e?? ??e?d?? e??a? se µ????.
• S???e?a
• G?a µ?a ??aµµ? e??a? //
• G?a p????? / /
• ?as???? t?µ?? 1-bit s?µ?t??
• 0 ?????? t?µ? 0.
• 1 ?????? t?µ? 1
• x ????st? t?µ?
• z as??det? s?µa. high impedance

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????µ??

• ??apa??stas? a???µ??
• ltsizegt ltbase_formatgtltnumbergt
• ltsizegt de???e? t?? a???µ? ap? bits
• ltbase_formatgt µp??e? ?a e??a? d, h, b, o
• ?ta? t? ltsizegt ?e?pe? t? µ??e??? ?a?????eta? ap?
  t?? compiler.
• 100 // 100
• 4b1111 // 15, 4 bits
• 6h3a // 58, 6 bits
• 6b111010 // 58, 6 bits
• 12h13x // 304x, 12 bits

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Operators

• Arithmetic - /
• Relational lt gt lt gt
• Equality !
• Logical !
• Bit-wise
• Shift ltlt gtgt
• Conditional x? yz
• Concatenation/Replication A,B 4A

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?e??d?????a S?ed?as??
?e???? s?st?µa ap?te?e?ta? ap? ta Leaf blocks p??
t?????? ??a pa??????a. ?e? ?p???e? program
counter st?? Verilog.
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?as??? Block Module
Name arith
module arith (out1, out2, in1, in2) output out1,
out2 input in1, in2 endmodule
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???te? e??? Module
Name arith1
module arith1 (bi_out, out, in1,
in2, in3) inout bi_out output out input in1,
in2 input in3 endmodule
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Modules vs Instances

• Instantiation e??a? ? d?ad??as?a d?µ??????a?
  a?t??e?µ???? ap? t? module.

module nand(out, a, b,) input a, b Output
out wire out out (a b) endmodule
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Primitives

• ?p?ped? ?????
• and, nand, or, nor, xor, xnor, not, buf
• ?a??de??µa
• and N25 (out, A, B) // instance name
• and 10 (out, A, B) // delay
• or 15 N33(out, A, B) // name delay

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?????? ???s?µ???s??

• timescale lttime_unitgt/lttime_precisiongt
• time_unit µ???da µ?t??s?? ??????
• time_precision e????st? ????? ß?µata ?at? t??
  p??s?µ???s?.
• ????de? ?????? s, ms, us, ns, ps
• lttimegt a?aµ??? ??a ????? lttimegt
• 5 a8h1a
• _at_lts?µagt a?aµ??? µ???? t? s?µa ?a a????e? t?µ?
• _at_ (posedge clk)
• _at_ (negedge clk)
• _at_ (a)

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Module Body
module test(a, b,) input aoutput b reg b wire
c always _at_(posedge a)begin b 2
a end always _at_(negedge a) begin b 2
c end not N1 (c, a) initial begin b
0 end endmodule

• Declarations
• always blocks. ?p??e? ?a
• pe????e? p??? ap? ??a
• initial. ?p??e? ?a pe????e?
• ??a ? ?a???a.
• primitives
• Instantiations

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??p?? µetaß??t?? st?? Verilog

• integer // a???µ??
• wire // ?a??d?? s??µa
• reg // register
• tri // tristate

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Wires

• S??d?ast??? ?????? (de? ??e? µ??µ?)
• G??f?? e?a?t?se??
• ?p??e? ?a pe??????e? ?a? ?d?a?te?a p???p????
  ??????

wire sum a b wire c sum b wire a d
wire sum ... assign sum a b
wire muxout (sel 1) ? a b wire op (a
((b) ? c d) (e))
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S??µata ?a? s??d?ast??? ??????

• module endmodule
• ????s? e?s?d?? - e??d??
• Concurrent statements

module adder(a, b, sum, cout) input a,
b output sum, cout wire sum a b wire
cout a b endmodule
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Registers (a???????a?? ??????)
reg a initial begin a 0 5 a 1 end

• St???e?a µ??µ??
• ??t? a?????? µe µetaß??t?? st? C
• ???? registers (??? wires) pa?????? t?µ? se
  initial ?a? always blocks.
• Synthesizable code
• ??a??se?? ???t?
• ??a??es? test bench
• Hold time

reg q always _at_(posedge clk) begin if (load)
q 2 d end
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Registers ?a? s??d?ast??? ??????
?? ? s????t?s? F() e??a? p???p???? t?te
reg out always _at_(in1 or in2 or in3) out lt
f(in1,in2,in3)
S??d?ast??? ?????? F()
in1
out
in1
in1
reg out always _at_(in1 or in2 or in3) out lt in1
(in2 in3)
?s?d??aµa
wire out in1 (in2 in3)
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Assignment

• blocking
• always _at_(posedge clk)
• begin
• a b
• c a // c pa???e? t?µ? t?? b
• end
• non blocking lt
• always _at_(posedge clk)
• begin
• a lt b
• c lt a // c pa???e? pa??? t?µ? t?? a
• end

b
a
c
a
c
b
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Assignment Example

• time 0 a 10 b
• time 10 c a
• a(t10) b(t0)
• c(t10) a(t10) b(t0)

10 time 10 a b time 10 c
a a(t10) b(t10) c(t10) a(t10) b(t10)
time 0 a lt 10 b time 0 c lt a a(t10)
b(t0) c(t0) a(t0)
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???s? ?a??st???s?? st?? Verilog

• Functional Verification (RTL Model)
• ? ?a??st???s? e??a? p??se???st???. ?.?.
• always _at_(posedge clk) d lt 10 q // FF µe 10
  µ???de? ?a??st???s?
• S?????? ?e????µe ?t? ? s??d?ast??? ?????? de?
  ??e? ?a??st???s?.p.?.
• wire a (b c) d // µ??? t?? ?e?t?????a ???
  ?a??st???s? p????
• ? ?a??st???s? ???s?µ?p??e?ta? ?????? st?
  testbench ??d??a ??a ?a ft?????µe ta inputs.
• Timing Verification
• ??a??t??? ???e p??? ??e? ?a??st???s?.
• S?????? ????µe timing verification se gate-level
  model t? ?p??? ft????eta? ap? ??a synthesis ? PnR
  tool.

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?a???e? ???t?? Module

• ?a input ?a? inout ????? t?p? wire µ?sa st?
  module
• Ta outputs µp??e? ?a ????? t?p? wire ? reg

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S??d?se?? µeta?? Instances

• ?e ß?s? t?? ??s?
• module adder(Sum, In1, In2)
• adder (A, B, C) // Sum A, In1 B, In2 C
• S?s?et????ta? ???µata
• module adder(Sum, In1, In2)
• adder (.In2(B), .In1(A), .Sum(C))
• // Sum C, In1 A, In2 B

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Buses
Name arith2
module arith2 (out, in1, in2) output 10
out input 10 in1, in2 endmodule
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Buses (cont)

• ?aµ?a d?af??? st? s?µpe??f???
• S?µß?se??
• high low
• msb lsb
• ???s??? st?? s??d?se?? e?t?? t?? module

module adder(a, b, sum, cout) input 70 a,
b output 70 sum output cout wire
80 tmp a b wire 70 sum
tmp70 wire cout tmp8 endmodule
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G????µ? ??d??a

• ? ?e?t?????a ???? module µp??e? ?a ???ste? µe
  d??f????? t??p???
• Behavioral (ep?ped? p?? ???t? st?? ??????)
• ?a??µ??a µe t?? C ? ??d??a? de? ??e? ?µes?
  s??s? µe t? hardware.
• p.?. wire a b c
• Gate level/structural (ep?ped? ???t? st?
  hardware)
• ? ??d??a? de???e? p?? p?a?µat??? ???p??e?ta? se
  p??e? ? ??????.
• p.?.
• wire sum a b
• wire cout a b

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Synthesizable Code

• ? Synthesizable ??d??a? µp??e? ?a ???e?
  synthesize ?a? ?a p????µe gate-level µ??t??? ??a
  ASIC/FPGA.
• p.?.
• wire 70 sum tmp70 8a
• wire cout tmp8
• Non-synthesizable ??d??a? ???s?µ?p??e?ta? µ???
  ??a p??s?µ???s? ?a? pet??ta? ?at? t?? d?ad??as?a
  t?? synthesys.
• p.?.
• initial begin
• a 0 b 0
• 5 a 1 b 1
• end

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Testing
Hierarchical Testing
- Block-level simulation
/ System-level
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???se???se?? ??a ??e??? s?st?? ?e?t?????a?
???s????s? 1

• Testbench top module p?? ???e? instantiate t?
  module p?? test????µe, d?µ?????e? t?? t?µ?? t??
  e?s?d?? t?? ?a? e????e? ?t? ?? ???d?? t??
  pa?????? s?st?? t?µ??.

???s????s? 2
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??a ap?? test bench
module adder(a, b, sum, cout) input a,
b output sum, cout wire sum a b wire
cout a b endmodule

• module test
• reg a, b
• wire s, c
• adder add0(a, b, s, c)
• initial begin
• a 0 b 0
• 5 display("a x, b x, s x, c x", a, b,
  s, c)
• a 1
• 5 display("a x, b x, s x, c x", a, b,
  s, c)
• b 1
• 5 display("a x, b x, s x, c x", a, b,
  s, c)
• a 0
• 5 display("a x, b x, s x, c x", a, b,
  s, c)
• end
• endmodule

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?et??t?? 8 bits
module counter(clk, reset, out) input
clk, reset output 70 out wire 70
next_value out 1 reg 70 out always
_at_(posedge clk) begin if (reset) out 2
8b0 else out 2 next_value end endmodule
module clk(out) output out reg out initial
out 1b0 always out 25 out endmodule
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?et??t?? 8 bits (2)
initial begin reset 1 _at_(posedge clk)
_at_(posedge clk) reset 2 0 _at_(posedge clk)
300 end endmodule
module test wire clk reg
reset wire 70 count clock
clk0(clk) counter cnt0(clk,
reset, count)
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?et??t?? 8 bits (3)

• counter.v
• clock.v
• test.v

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??a?efa?a??s?!

• ??? t?p?? statements
• initial
• always
• ??s?d?? - ???d??
• input, output
• ?p?te??sµata
• display
• Cadence waves

• S??d?ast??? ??????
• wire
• ????????a?? ??????
• reg
• Buses
• highlow
• ?a??ste??se??
• t
• _at_(posedge )