Pr

1
General Interconnection design
PCI R Reg
PCI W Reg
PCI R/W Reg
MB R Reg
MB W Reg
Mux
32
LAD310
MB R/W Reg
PCI R /MB R Reg
128
MBD1270
PCI R /MB W Reg
PCI R /MB R/W Reg
PCI W /MB R Reg
Mux
PCI W /MB W Reg
Mux
PCI W /MB R/W Reg
Mux
PCI R/W /MB R Reg
PCI R/W /MB W Reg
Mux
PCI R/W /MB R/W Reg
Mux
2
10
I/O Control Register
16
PCI Translation Base
16
MBus Upper Memory Address
16
MBus Lower Memory Address
16
MBus Translation Base
16
MBus Error Register
Data Busses
32
128
PIO PCI to MB register
32
LAD310
128
PIO MB to PCI register
Mux
32
Broadcast Status Register
32
Crate Master Register
32
Internal Control Register
32
Internal Request Register
128
MBD1270
32
Internal Test Register
8
User Output Register
8
User Input Register
32
Geographic Address Register
32
Mapper Array
128
32
Data FIFO
10
Address FIFO
PCI In Address Register
32
PCI Out Address Register
32
3
Memory
Local bus
Magic Bus
Group
Base Address
Offset
Type
Width (bits)
Depth (Words)
accesses
Function
Width (bits)
Depth (Words)
accesses
I/O Control Register
0x0000
Register
LBA 0
None
R/W
10 b
1
I/O Control
PCI Translation Base
0x0010
Register
LBA 0
None
R/W
16 b
1
MBus Upper Memory Address
0x0014
Register
LBA 0
None
R/W
16 b
1
MBus Lower Memory Address
0x0018
Register
LBA 0
None
R/W
16 b
1
PIO Configuration
MBus Translation Base
0x001C
Register
LBA 0
None
R/W
16 b
1
MBus Error Register
0x0020
Register
LBA 0
None
R/W
16 b
1
PIO PCI to MB register win A/B
?
LBA 1/2
Register
R
W
128 b
32 b
1
1
PIO Transfers
PIO MB to PCI register
?
LBA 1
Register
W
R
128 b
32 b
1
1
0x010C
Broadcast Status Register
Register
LBA 0
None
R
32 b
1
0x0110
Crate Master Register
Register
LBA 0
None
R/W
32 b
1
0x0114
Register
LBA 0
None
R/W
32 b
1
Scaler Register
Internal Control Register
0x0130
Register
LBA 0
None
R/W
32 b
1
TSI Registers
0x0134
Internal Request Register
Register
LBA 0
None
R
32 b
1
None
R/W
32 b
1
0x013C
Internal Test Register
Register
LBA 0
0x0140
User Output Register
Register
LBA 0
None
R/W
8 b
1
0x0144
Register
None
R
8 b
1
User Input Register
LBA 0
0x0148
Register
None
R
32 b
1
Geographic Address Register
LBA 0
0x1000
RAM
None
R/W
32 b
Mapper Registers
Mapper Array
LBA 0
0x400
Data FIFO
FIFO
128 b
0x1000
W
32 b
0x4000
R
LBA 0
?
Data storage
Address FIFO
FIFO
10 b
0x1000
W
10 b
0x1000
R
LBA 0
?
4
10
I/O Control Register
16
PCI Translation Base
16
MBus Upper Memory Address
16
MBus Lower Memory Address
16
MBus Translation Base
16
MBus Error Register
Data Busses
32
128
PIO PCI to MB register
32
LAD310
128
PIO MB to PCI register
32
32
Broadcast Status Register
32
Crate Master Register
32
Scaler Register
32
Internal Control Register
128
MBD1270
32
Internal Request Register
32
Internal Test Register
8
User Output Register
8
User Input Register
32
Geographic Address Register
32
Mapper Array
128
32
Data FIFO
10
Address FIFO
PCI In Address Register
32
PCI Out Address Register
32
5
fifo_full
mbdlt127..0gt
XCV405E
fifo_empty
mbalt31..0gt
dma_access
mod_donelt18..0gt
ecl_access
ev_loadedlt3..0gt
mb_access
n_bossreq
pci_access
n_dstrobe
DISPLAY
plx_access
n_bossin
vme_access
bossgrin
n_bossout
vme_activity
bossgrout
n_ddonein
mb_clk_in
doneout
gmb_clk_in
n_ddoneout
pci_clk_in
n_rd_wr
CLOCK
gpci_clk_in
n_startload
MAGIC BUS
n_bufin1
n_vme_rst_out
n_bufin0
n_vme_rst_in
n_bufout1
n_sw_rst_off
n_bufout0
RESET
n_sw_rst_on
fifoemptyin
n_led_reset
n_fifoemptyout
n_resetin
n_ads
n_resetout
ale
n_mbmaster
n_bigend
n_crmaster
n_blast
n_mben
breqi
n_mbdatdir
breqo
n_mbadddir
n_bterm
n_den
vbd_start_req
dmpaf_eot
vbddone
dplt3..0gt
l2_answer_ready
n_dt_r
ext_tsi_int_req
ladlt31..0gt
j2_resv_outlt7..0gt
n_lbelt3..0gt
j2_resv_inlt7..0gt
TSI
lhold
n_gap
lholda
n_galt4..0gt
LOCAL BUS
n_lw_r
test_outlt3..0gt
n_lserr
n_ready
tsi_outlt31..0gt
n_wait
n_linto
test_ptlt31..0gt
n_dacklt1..0gt
TEST POINTS
n_dreqlt1..0gt
n_ccs
lclk
n_linti
n_lb_reset
useri_llocki
usero_llocko
pmereq
6
fifo_full
fifo_empty
dma_access
Rst Display Clock
ecl_access
XCV405E
mb_access
mbdlt127..0gt
pci_access
mbalt31..0gt
MAGIC BUS
plx_access
mod_donelt18..0gt
vme_access
Display management
ev_loadedlt3..0gt
n_bossreq
vme_activity
n_dstrobe
mb_clk_in
n_bossin
gmb_clk_in
bossgrin
Address translator
pci_clk_in
n_bossout
gpci_clk_in
bossgrout
Address decoder
Clock management
n_ddonein
doneout
n_vme_rst_out
n_ddoneout
Add mapper
n_vme_rst_in
n_rd_wr
n_sw_rst_off
n_startload
n_sw_rst_on
n_bufin1
n_led_reset
n_bufin0
State machine
Reset management
n_bufout1
n_bufout0
Add translator
fifoemptyin
n_fifoemptyout
n_resetin
n_ads
n_resetout
ale
n_mbmaster
n_bigend
n_crmaster
LOCAL BUS INTERFACE
n_blast
n_mben
breqi
n_mbdatdir
breqo
n_mbadddir
n_bterm
n_den
dmpaf_eot
dplt3..0gt
n_dt_r
ladlt31..0gt
n_lbelt3..0gt
lhold
Address decoder
TSI Block
PIO Block
lholda
vbd_start_req
n_lw_r
vbddone
n_lserr
l2_answer_ready
n_ready
ext_tsi_int_req
n_wait
j2_resv_outlt7..0gt
TSI registers
PIO registers
n_linto
j2_resv_inlt7..0gt
n_dacklt1..0gt
n_gap
State machine
n_dreqlt1..0gt
n_galt4..0gt
n_ccs
test_outlt3..0gt
lclk
n_linti
tsi_outlt31..0gt
State machine
State machine
n_lb_reset
useri_llocki
usero_llocko
pmereq
test_ptlt31..0gt
TEST POINTS
7
LOCAL BUS INTERFACE
32
PCI In Address Register
pci_en_wr_mem_1
n_ads
pci_ en_rd_mem_1
32
Address decoder
ale
pci_ en_buf_mem_1
PCI Out Address Register
Combinatorial Logics
ladlt31..0gt
pci_ en_buf_mem_n
data_inlt31..0gt
pci_add_inlt31..0gt
data_outlt31..0gt
State machine
pci_add_outlt31..0gt
pci_ en_wr
pci_ en_rd
n_bigend
n_blast
breqi
breqo
n_bterm
n_den
dmpaf_eot
int_pci_mb
dplt3..0gt
n_dt_r
int_mb_pci
n_lbelt3..0gt
lhold
dma_pci_mb
lholda
n_lw_r
dma_pci_mb
n_lserr
n_ready
n_wait
n_linto
n_dacklt1..0gt
n_dreqlt1..0gt
n_ccs
lclk
n_linti
n_lb_reset
useri_llocki
usero_llocko
pmereq
8
MAGIC BUS INTERFACE
32
Magic Bus In Address Register
mb_en_wr_mem_1
mb_en_rd_mem_1
32
Address decoder
mb_en_buf_mem_1
Magic Bus Out Address Register
Combinatorial Logics
mb_en_buf_mem_n
mbalt31..0gt
mb_add_inlt31..0gt
mb_add_outlt31..0gt
State machine
mb_en_wr
mb_en_rd
mod_donelt18..0gt
ev_loadedlt3..0gt
n_bossreq
n_dstrobe
int_pci_mb
n_bossin
bossgrin
int_mb_pci
n_bossout
bossgrout
dma_pci_mb
n_ddonein
doneout
dma_pci_mb
n_ddoneout
n_rd_wr
n_startload
n_bufin1
n_bufin0
n_bufout1
n_bufout0
fifoemptyin
n_fifoemptyout
n_resetin
n_resetout
n_mbmaster
n_crmaster
n_mben
n_mbdatdir
n_mbadddir
mbdlt127..0gt
data_inlt127..0gt
data_outlt127..0gt
9
PIO Block
PIO registers
10
I/O Control Register
State machine
16
PCI Translation Base
16
MBus Upper Memory Address
data_outlt127..0gt
data_inlt127..0gt
16
MBus Lower Memory Address
pci_en_wr_io_ctrl_reg
pci_en_rd_io_ctrl_reg
pci_en_wr_pci_trans_base
16
MBus Translation Base
pci_en_rd_pci_trans_base
pci_en_wr_mb_up_mem_add
pci_en_rd_mb_up_mem_add
pci_en_wr_mb_low_mem_base
16
MBus Error Register
pci_en_rd_mb_low_mem_base
pci_en_wr_mb_err_reg
pci_en_rd_mb_err_reg
pci_en_wr_pci_to_mb_reg
32
128
PIO PCI to MB register
pci_en_rd_pci_to_mb_reg
mb_en_wr_pci_to_mb_reg
mb_en_rd_pci_to_mb_reg
pci_en_wr_mb_to_pci_reg
128
PIO MB to PCI register
32
pci_en_rd_mb_to_pci_reg
mb_en_wr_mb_to_pci_reg
mb_en_rd_mb_to_pci_reg
Address Translator
mb_add_inlt31..0gt
mb_add_outlt31..0gt
fifoemptyin
pci_add_inlt31..0gt
pci_add_outlt31..0gt