Sequential Logic 2

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Sequential Logic 2

• Anselmo Lastra

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Administrative

• Make sure you have access to lab and ModelSim for
  homework
• I hear there were some ModelSim license problems
• How are things going?
• Problems understanding?
• Too easy / too hard?

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Verilog

• Forgot to mention useful for tests
• stop
• Stops the simulation
• So you can hit run all button to run complete
  sim program

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Topics

• Flip-Flops

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Review D-type Latch

• No illegal state

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Problem of Transparency

• As long as C high, state can change
• Whats problem with that?

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Effects of Transparency

• Output of one latch may feedback
• So more state changes may happen
• Depends on gate delays
• Want to change latch state once
• Depending on inputs at time of clock

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Flip-Flops

• Ensure one transition
• Two major types
• Master-Slave
• Two stage
• Output not changed until clock disabled
• Edge triggered
• Change happens when clock level changes

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Master-Slave Flip-Flop

• Either R (master) or L (slave) is enabled, not
  both

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Timing Diagram

• Trace the behavior
• Note illegal state

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Still Have SR Illegal State

• Can use similar approach as for D

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JK Master-Slave FF

• Output gates J K so if JK both high, next Q is
  inverse of current one

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Have We Fixed Problem?

• Output no longer transparent
• Combinational circuit can use last values
• New inputs appear at latches
• Not sent to output until clock low
• But changes at input of FF when clock high
  trigger next state
• Transient state where S goes high caused by gate
  delays
• As clock faster, more problems
• Have to guarantee circuit settles while clock low

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Edge-Triggered Flip-Flops

• New state latched on clock transition
• Low-to-high or high-to-low
• Changes when clock high are ignored
• Note Master-Slave also called pulse triggered

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D-Type Edge Triggered
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Negative edge D-type

• From WebPACK

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Behavioral
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Flip-Flop Timing

• Draw on board
• Setup time time that D must be available before
  clock edge
• Hold time time that D must be stable after
  clock edge
• Propagation delay time after edge when output
  is available

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Edge-Triggered JK

• Same truth table as other JK flip-flop, but edge
  triggered

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Standard Symbols Latches

• Circle at input indicates negation

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Symbols Master-Slave

• Inverted L indicates postponed output
• Circle indicates whether enable is positive or
  negative

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Symbols Edge-Triggered

• Arrow indicates edge trigger

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Characteristic Tables

• Can describe function of flip flops by
  considering state
• Current state
• Next state at clock pulse governed by inputs
• Concept of state at times useful

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JK and SR Flip-Flops
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T Flip-Flop

• Similar to D, except T input governs whether
  state changes or not
• Instead of whether Q is 1 or 0

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Clock Gating

• Can gate clocks (like to keep any FF from
  changing states)
• However, can cause clock skew
• Clock skew also caused by wire lengths over chip

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Direct Inputs

• Set/Reset independent of clock
• Direct set or preset
• Direct reset or clear
• Often used for power-up reset

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Verilog for Sequential

• Add some new Verilog to describe sequential
  circuits
• Can use latches and flip-flops from library in
  schem. capture or Verilog
• And connect them
• But more productive to write higher-level Verilog
  description

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Register Data Type

• Like wire but value is retained over time
• Often causes latch or FF to be synthesized
• Examples
• reg state
• reg 150 addr

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Always Block

• Example
• always _at_ (Reset or Reset)
• statement
• Sensitivity list determines what might affect
  statements
• Could think of it as statement is run when one
  of nets in sensitivity list changes value
• Example next

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Flip-Flop Example

• module dff_v(CLK, RESET, D, Q, Q_n)
• input CLK, RESET, D
• output Q, Q_n
• reg state
• assign Q state
• assign Q_n state
• always _at_(posedge CLK or posedge RESET)
• begin
• if (RESET)
• state lt 0
• else
• state lt D
• end
• endmodule

negedge also used
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This is Not Software

• Dont assign to same reg in more than one always
  block
• The always blocks are concurrent
• Doesnt make sense to set reg from two signals
• Assignments in always blocks should be
  non-blocking
• You usually dont mean sequential execution

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Analysis of Sequential Circuits

• Earlier we learned how to analyze combinational
  circuits
• Now extend to synchronous sequential
• Include time
• Time will be governed by clock, so discrete
• Well use state tables and state diagrams

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Input Equations

• Can describe inputs to FF with logic equations

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Another Example
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Time is Implied

• If circuit is synchronous, time implied as
  sequence of clock ticks
• Note that last circuit used
• Previous state to determine next state
• State and inputs to determine output

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State Table

• For last example
• Truth table with state added

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Two Dimensional Table

• Same thing, different layout

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Sequential Circuit Types

• Moore model outputs depend on states

• Mealy model also depend on inputs

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Today

• Flip-Flops
• Verilog always statement
• Notion of state and next state

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Next Time

• State Diagrams
• Registers