EDUSAT SESSION FOR ADVANCED MICROPROCESSOR EC54

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EDUSAT SESSION FOR ADVANCED MICROPROCESSOR
(EC54) Date 16.12.2005 Session XI Topic 80486
and Pentium Faculty Anita Kanavalli MSRIT
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Introduction to 80486

• 80386 microprocessor is 32 bit processor
• Its Features are
• Upward compatible with 80386
• MMU
• Virtual Memory
• software protection
• also available 80486DX 80486SX

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Introduction to 80486

• 80486 microprocessor is 32 bit processor
• Its Features are
• it is 162 pin grid array
• Important pins
• A20M- address bit 20 mask allows to wrap its
  address around from location 000FFFFFH to
  0000000H
• AHOLD- address hold input places to high
  impedance state
• BLAST- burst last output indicate completion of
  burst cycle

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Introduction to 80486

• BRDY- burst ready input used to signal that the
  burst cycle is complete
• DP3-DP0-data parity I/O provides even parity for
  a write operation and check parity for read
  operation
• EADS- external address strobe input is used with
  AHOLD to signal that an external address is used
  to perform a cache invalidation cycle
• FLUSH- cache input forces the microprocessor to
  erase the contents of its 8K byte internal cache

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Introduction to 80486

• IGNNE- ignore numeric error causes the
  coprocessor to ignore floating point errors and
  to continue processing data
• PWT-page write through output indicates the
  state of the PWT attribute bit in the page table
  entry or the page directory entry
• RDY- ready input indicates that a non burst bus
  cycle is complete

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Basic architecture

• Contain eight general purpose 32 bit registers
  EAX, EBX,ECX,EBP,EDI,ESI and ESP
• 16 bit registers as same as 8086
• The memory is 4G bytes
• Contains global,local and IDT
• MMU and paging scheme is supported

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Memory System

• The memory location starts 00000000H to
  FFFFFFFFH
• Internal memory of 8K byte in the form of cache
• includes the parity storage-parity checker/
  generator
• Cache is organized as 4 way set associative
• The memory has four banks
• The control register CR0 is used to control the
  cache
• uses burst cycle to fill the cache

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Memory System

• Paging system can be disabled
• two new bits exist in page table entry
• PWT and PCD for control caching
• PCD0 cache is enabled otherwise disabled
• There are three cache test registers

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Pentium

• Packaged in 237 pin PGA
• There are some system management related pins
• Memory is 4G bytes in size
• uses 64 bit data bus
• there are 8 banks 512 M bytes of data
• each byte stored with a parity
• has internal parity generate and check

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Pentium

• 64 bit wide memory is helpful double precision
  numbers
• the number can be retrieved in one read cycle
• there are 8 bank enable signals BE7-BE0
• new feature in pentium is parity check for the
  address bus
• a 32 bit wide memory system is connected using a
  multiplexer
• I/O system is similar to other systems, appears
  on A15-A3 lines

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Pentium

• Uses branch prediction logic
• contains two 8K byte cache one data and other
  instruction
• has a superscalar architecture
• has three execution units
• one for floating point operations
• U-pipe and V-pipe for integer instructions
• can execute two integer and one MMX instruction
  together

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Pentium

• Control registers CRO-CR4
• it has bits for cache disable, not write
  through, alignment mask, write protect etc
• The flag register has new bits like
  identification flag, VIP,VIF and AC
• BIST is accessed on power up by placing a logic
  1 on INIT while the RESET pin changes from 1 to 0

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Pentium

• 4M byte memory pages
• there is no page entry in the linear address
• no page tables instead the page directory
  addresses a 4M byte memory page
• System memory management mode is like protected
  mode functions like a manager

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Questions

• Compare the register sets or 386 and 486
• Which pins are used for parity checking
• How much memory can be addressed by pentium
• Describe the descriptors and selectors