CPU Design

1
CPU Design

• How instructions are interpreted and executed in
  the engine of the computer system

2
Instruction Set Architecture (ISA)

• Instruction set architecture of a computer is the
  interface between the hardware and the software.
• It includes everything a machine (assembler)
  programmer need to know to write a program for
  the computer
• User registers where programs can store temporary
  values
• Program Counter a special register used to
  store the address of the next instruction to be
  executed.
• Memory system

3
ISA of a Small Computer

• In this course, we are going to use a minimal
  computer as a complete example to show typical
  computer organization and its implementation.
• It has only one user register, A, used as an
  accumulator for arithmetic and logic operations
• It has a small memory system with a 16x8 RAM

4

• ISA of the computer is

5

• A simple program for our computer
• g LDA z 0000 0010 1100 load z
  into register A 2C
• BEZ h 0001 0101 1001 branch
  to h, if A0 59
• LDA x 0010 0010 1010 load x
  into register A 2A
• ADD y 0011 0111 1011 add y
  into register A 7B
• STA x 0100 0011 1010 store
  register A to x 3A
• LDA z 0101 0010 1100 load z
  into register A 2C
• ADD w 0110 0111 1101 add w
  into register A 7D
• STA z 0111 0011 1100 store
  register A to z 3C
• JMP g 1000 0100 0000 jump
  to g 40
• h HLT 1001 0001 0000 halt
  the machine 10
• x 0 1010 0000 0000
  variable x 00
• y 15 1011 0000 1111
  variable y 0F
• z 3 1100 0000 0011
  variable z 03
• w -1 1101 1111 1111
  variable w FF

6
Components of CPU

• A CPU in general consists of
• a datapath which includes
• all the registers
• an arithmetic login unit (ALU) to perform
  operations
• an internal bus to connect them
• a control unit to control the instruction fetch
  and execution. It includes
• a finite state machine for the different states
  of instruction fetch and execution
• a control logic unit to provide control signals

7
Registers in CPU

• The CPU also includes the registers
• which is not part of the ISA,
• But they are necessary for realize basic
  operations of instruction fetch and execution
• Registers not seen in ISA
• Instruction Register (IR) to hold the opcode of
  the instruction fetched and currently being
  executed
• Memory Address Register (MA) to hold
• the address of the instruction to fetch
• the address of the data to be read and write
• Data Register (B) to hold
• the data from memory for arithmetic and logic
  operations with register A
• the data to written into the memory

8
Instruction Fetch and Execution

• Instructions are fetched and executed through
  many steps.
• Each step takes one clock cycle time
• Each step corresponds to a state of a finite
  state machine.
• Instruction fetch cycles
• the cycles to fetch instruction from the memory
• They are common to all instructions.
• Instruction execution cycles
• the cycles to execute the instruction fetched
• Different instructions will go through different
  steps (states) in their execution.

9

• The typical instruction fetch and execution
  cycles are as follows

10

• Instruction fetch and execution of our computer

fetch1
T0
T1
fetch2
NOP
ADD
HLT
T2
LDA1
STA1
JMP1
BEZ1
AND1
ADD1
HLT1
T3
AND2
ADD2
11

• While the instruction fetch and execution cycles
  can be regarded a finite state machine, it
• has too many states, given the large number of
  instructions.
• Not all states are used for a particular
  instruction
• for each instruction, only one or two states are
  used after it is fetched
• We can reduce the number of states significantly
  if we
• use timing sequences, T0, T1, T2, and T3, as the
  states and
• use instruction signals such as NOP, HLT, ,
  ADD, as the inputs to finite state machine.

12

• An instruction fetch and execution takes 3 or 4
  cycles in total
• two cycles, named T0 and T1, for fetching the
  instruction (common to all instructions)
• one or two cycles, named T2 and T3, to execute
  the instruction (different for different
  instructions)
• We can use a finite state machine with 4 states
  to control the instruction fetch and execution.
• four states T0, T1, T2, and T3
• external inputs eight instruction signals

13

• The timing control finite state machine is as
  follows

NOP
T1
HLTLDASTAJMPBEZAND ADD
ALL

T2
LDASTAJMPBEZ

T0
ANDADD

T3
14

• Here, NOP, HLT, LDA, STA, JMP, BEZ, AND and ADD
  are the signals representing the eight
  instructions.
• These signals can be obtained by decoding the
  contents of IR after the instruction is fetched.
• ALL NOPHLTLDASTAJMPBEZANDADD
• Once this finite state machine is implemented, we
  can combine
• the timing state signals, T0, T1, T2, and T3
• the instruction signals, NOP, , and ADD
• to form the required instruction fetch and
  execution cycles.
• For example, ADD1 T2ADD, ADD2T3ADD

15
Micro-Operation Design

• Each step of instruction fetch and execution is
  realized by certain register-level
  micro-operations.
• These micro-operations can be specified by
  register transfer notations in a table called
  instruction event table.

16

• Instruction event table of our computer

17

• The condition for the register-transfers in an
  entry is the Boolean AND of the timing state
  (column) and the instruction signal (row).
• For example, the condition for register transfer
  A?AB is ADDT2
• If a register-transfer appeas in many entries,
  the condition for it is the Boolean OR of all the
  conditions of the corresponding entries.
• For example, the condition for register transfer
  MA?PC is NOPT0 HLTT0 ADDT0

18
Datapath Design

• The datapath of CPU is determined by all the
  register-transfers in the instuction event table.
  It consists of
• all the registers required
• an arithmetic logic unit (ALU) for all the
  micro-operations specified in the table
• a bus system for all the register-transfers
  specified in the table

19

• Datapath of our computer

Memory
ZERO
MEM2BUS
WR
A
ALU
LD-A
MA
ALU2BUS
B
LD-MA
MA2BUS
LD-B
PC
PCLD
PCG
PC2BUS
IR
LD-IR
20

• Bus control signals to allow data to appear on
  bus
• MEM2BUS
• ALU2BUS
• MA2BUS
• PC2BUS
• Registers A, B, IR, MA are ordinary registers
  with load control signals, LD-A, LD-B, LD-IR,
  LD-MA connected their G inputs
• A and B are 8-bit registers
• IR and MA are 4-bit registers

21

• Register PC is a 4-bit up counter with its
  control signals
• PCLD connected to LD inputs for parallel load
• PCG connected to G input
• PCG LD-PC PCINC
• ALU has its own control signals S0, L/A, C0
• L/A to select logic or arithmetic mode
• C0 for the carry-in bit for the Adder
• Memory has a write control
• WR write the memory when WR1

22

• List of Control Points
• datapath control points
• WR write mode of memory
• MEM2BUS, ALU2BUS, PC2BUS, MA2BUS
• S0, CI, L/A control points of ALU
• PCLD load mode for the up-counter of PC
• register load control points (connected to G
  input)
• LD-A, LD-B, LD-MA, LD-IR to load the register
• LD-PC to load parallel data into the counter
• PCINC to increment the counter
• special control points
• STOP to stop the clock for Halt instruction

23

• Implementation of datapath of our computer