Wafer thinning using SOI technology

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Wafer thinning using SOI technology

• Y. Sugimoto
• 2005/4/13

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Thin CCD wafer

• Wafer thickness less than 50 mm is desirable for
  the ILC vertex detector
• Thickness of epi-layer should be less than 20 mm
  for FPCCD to keep pixel occupancy low
• 20 mm wafer can be made but its flatness is poor
• Standard etching technique gives twafertepi
• SOI technology could achieve 50 mmgt twafer gt tepi

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CCD wafers partially thinned down to 20 mm
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Thinning using SOI
SOI Substrate
Substrate
Epi. growth
Epi. growth
Process
Process
Etching
Etching
Standard method
Using SOI