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week3-1

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Inverter: after transition time, what is the current? Modern VLSI ... Use tub ties to connect tub to power rail. Use enough to create low-voltage connection. ... – PowerPoint PPT presentation

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Title: week3-1


1
  • Lectures 6, 7 and 8
  • Transistor Function
  • Jan. 17, 20 and 22, 2003

2
Topics
  • Previous
  • Transistor as switch
  • Basic fabrication steps.
  • Basic Transistor function
  • Basic transistor behavior.

3
Transistor structure
  • n-type transistor

4
Gate voltage and the channel
Vs0 V
Vt 0.7 V
gate
drain
source
Vgs gt Vt
Id
gate
drain
source
Vgs lt Vt
5
Drain current characteristics
6
Example 1
  • V gs keeps 1.5V, 2.5V, 5V
  • V ds changes

7
Drain current
  • Linear region (Vds lt Vgs - Vt) !!!
  • Id k (W/L)(Vgs - Vt)Vds - 0.5 Vds2)
  • Saturation region (Vds gt Vgs - Vt)
  • Id 0.5k (W/L)(Vgs - Vt) 2
  • Text book is wrong!!!

8
What is related to the characteristics
  • W/L ratio!!!
  • V between Drain and Source
  • V between Gate and Source
  • Threshold voltage
  • Material

9
Transistor layout
  • n-type (tubs may vary)

L
w
10
0.5 ?m transconductances
  • From a MOSIS process
  • n-type
  • kn 73 ?A/V2
  • Vtn 0.7 V
  • p-type
  • kp 21 ?A/V2
  • Vtp -0.8 V

11
Current through a transistor
  • Use 0.5 ?m parameters. Let W/L 3/2. Measure at
    boundary between linear and saturation regions.
  • Vgs 2V
  • Id 0.5k(W/L)(Vgs-Vt)2 93 ?A
  • Vgs 5V
  • Id 1 mA

12
Explanation
  • When V gs 2V, can current go beyond 93 uA (when
    V ds changes)?

13
Example 2
  • When Vgs 2 V and V ds 2 V and 1.2 V
    respectively, calculate the I ds?
  • W/L 8
  • Kn 73 uA/V2

14
Example 3
  • Inverter when transition time, what is the
    current? (important example)
  • How N and P work?
  • Inverter after transition time, what is the
    current?

15
Questions
  • What is the real carrier in N transistor?

16
Gate voltage and the channel
Vs5 V
Vt -0.8 V
gate
drain
source
Vgs gt Vt
Id
gate
drain
source
Vgs lt Vt
17
Questions
  • What is the real carrier in P transistor?

18
Transistor and digital Logic
  • Combinational logic
  • Depend on transistor inverter
  • Sequential logic
  • Depend on transistor inverter

19
Drain current characteristics
20
Review
  • N and P transistors as switches
  • Fabrication process
  • Current Characteristics of N and P transistors

21
Example 4
22
  • Lecture 9
  • Transistor Parasitics Latch Up
  • Jan. 24, 2003

23
Topics
  • Transistor and basic fabrication steps.
  • Basic Transistor function
  • Basic transistor behavior.
  • Latch up.

24
Basic transistor parasitics
  • Gate to substrate, also gate to source/drain.
  • Source/drain capacitance, resistance.

25
Basic transistor capacitance
  • Gate capacitance Cg. Determined by active area.
  • Source/drain overlap capacitances Cgs, Cgd.
    Determined by source/gate and drain/gate
    overlaps. Independent of transistor L.
  • Cgs Col W
  • Gate/bulk overlap capacitance.

26
Transistor gate capacitance
  • Gate-source/drain overlap capacitance

gate
source
drain
overlap
27
Transistor source/drain parasitics
  • Source/drain have significant capacitance,
    resistance.
  • Measured same way as for wires.
  • Source/drain R, C may be included in Spice model
    rather than as separate parasitics.

28
Transistor Resistance
  • RU/I
  • Future topic

29
Latch-up
  • CMOS ICs have parasitic silicon-controlled
    rectifiers (SCRs).
  • When powered up, SCRs can turn on, creating
    low-resistance path from power to ground. Current
    can destroy chip.
  • Early CMOS problem. Can be solved with proper
    circuit/layout structures.

30
Parasitic SCR
circuit
I-V behavior
31
Parasitic SCR structure
32
Solution to latch-up
  • Use tub ties to connect tub to power rail. Use
    enough to create low-voltage connection.

33
Tub tie layout
p
metal (VDD)
p-tub
34
Question
Why these tub ties are needed?
35
(No Transcript)
36
(No Transcript)
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