Designing Combinational Logic Circuits

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Designing CombinationalLogic Circuits
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Combinational vs. Sequential Logic
Combinational
Sequential
Output
(
)
f
In, Previous In
Output
(
)
f
In
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Static CMOS Circuit
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Static Complementary CMOS
VDD
In1
PMOS only
In2
PUN

InN
F(In1,In2,InN)
In1
In2
PDN

NMOS only
InN
PUN and PDN are dual logic networks
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NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled
by its gate signal NMOS switch closes when switch
control input is high
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PMOS Transistors in Series/Parallel Connection
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Threshold Drops
VDD
VDD
PUN
S
D
VDD
D
S
0 ? VDD
0 ? VDD - VTn
VGS
VDD ? 0
PDN
VDD ? VTp
VGS
S
D
VDD
S
D
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Complementary CMOS Logic Style
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Example Gate NOR
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Example Gate NAND
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Stick Diagrams
Contains no dimensions Represents relative
positions of transistors
Inverter
NAND2
Out
Out
In
A
B
GND
GND
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NOR GATE IN DEPLETION LOAD TOPOLOGY
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Complex CMOS Gate
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Complex CMOS Gate
OUT D A (B C)
A
D
B
C
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Constructing a Complex Gate
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Stick diagram
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Minimize area-Eulers path
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Stick Diagrams-minimize area-Eulers path-EXAMPLES
Logic Graph
A
C
j
B
X C (A B)
C
i
A
B
A
B
C
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Two Versions of C (A B)
C
A
B
A
B
C
VDD
VDD
X
X
GND
GND
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Consistent Euler Path
X
C
VDD
i
X
A
B
j
A
B
C
GND
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OAI22 Logic Graph
X
PUN
A
C
C
D
B
D
VDD
X
X (AB)(CD)
C
D
A
B
A
B
PDN
A
GND
B
C
D
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Example x abcd
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Multi-Fingered Transistors
One finger
Two fingers (folded)
Less diffusion capacitance
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XOR CMOS Gate
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Properties of Complementary CMOS Gates Snapshot
High noise margins

V
and
V
are at
V
and
GND
, respectively.
OH
OL
DD
No static power consumption

There never exists a direct path between
V
and
DD
V
(
GND
) in steady-state mode
.
SS
Comparable rise and fall times
(under appropriate sizing conditions)
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CMOS Properties

• Full rail-to-rail swing high noise margins
• Logic levels not dependent upon the relative
  device sizes ratioless
• Always a path to Vdd or Gnd in steady state low
  output impedance
• Extremely high input resistance nearly zero
  steady-state input current
• No direct path steady state between power and
  ground no static power dissipation
• Propagation delay function of load capacitance
  and resistance of transistors

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Ratioed Logic
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Active Loads
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Pseudo-NMOS
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RATIOED LOGIC
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Improved Loads
V
V
DD
DD
M1
M2
Out
Out
A
A
PDN1
PDN2
B
B
V
V
SS
SS
Differential Cascode Voltage Switch Logic (DCVSL)
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DCVSL Example
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Transistor Sizing

4 4
2 2
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Transistor Sizing a Complex CMOS Gate
B
8
6
4
3
C
8
6
4
6
OUT D A (B C)
A
2
D
1
B
C
2
2
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Switch Delay Model
Req
A
A
NOR2
INV
NAND2
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Input Pattern Effects on Delay

• Delay is dependent on the pattern of inputs
• Low to high transition
• both inputs go low
• delay is 0.69 Rp/2 CL
• one input goes low
• delay is 0.69 Rp CL
• High to low transition
• both inputs go high
• delay is 0.69 2Rn CL

Rn
B
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Delay Dependence on Input Patterns
AB1?0
A1 ?0, B1
A1, B1?0
Voltage V
time ps
NMOS 0.5?m/0.25 ?m PMOS 0.75?m/0.25 ?m CL
100 fF
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Fan-In Considerations
A
Distributed RC model
(Elmore delay) tpHL 0.69 Reqn(C12C23C34CL)
Propagation delay deteriorates rapidly as a
function of fan-in quadratically in the worst
case.
B
C
D
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tp as a Function of Fan-In
Gates with a fan-in greater than 4 should be
avoided.
tp (psec)
tpLH
fan-in
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tp as a Function of Fan-Out
All gates have the same drive current.
tpNOR2
tpNAND2
tpINV
tp (psec)
Slope is a function of driving strength
eff. fan-out
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tp as a Function of Fan-In and Fan-Out

• Fan-in quadratic due to increasing resistance
  and capacitance
• Fan-out each additional fan-out gate adds two
  gate capacitances to CL
• tp a1FI a2FI2 a3FO

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Fast Complex GatesDesign Technique 1

• Transistor sizing
• as long as fan-out capacitance dominates
• Progressive sizing

Distributed RC line M1 gt M2 gt M3 gt gt MN (the
FET closest to the output is the smallest)
InN
MN
In3
M3
In2
M2
Can reduce delay by more than 20 decreasing
gains as technology shrinks
In1
M1
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Fast Complex GatesDesign Technique 2

• Transistor ordering

critical path
critical path
0?1
charged
charged
In1
1
In3
M3
M3
1
In2
1
In2
M2
discharged
M2
charged
1
In3
discharged
In1
M1
charged
M1
0?1
delay determined by time to discharge CL, C1 and
C2
delay determined by time to discharge CL
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Fast Complex GatesDesign Technique 3

• Alternative logic structures

F ABCDEFGH
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Fast Complex GatesDesign Technique 4

• Isolating fan-in from fan-out using buffer
  insertion

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Fast Complex GatesDesign Technique 5

• Reducing the voltage swing
• linear reduction in delay
• also reduces power consumption
• But the following gate is much slower!
• Or requires use of sense amplifiers on the
  receiving end to restore the signal level (memory
  design)

tpHL 0.69 (3/4 (CL VDD)/ IDSATn )
0.69 (3/4 (CL Vswing)/ IDSATn )
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Pass-TransistorLogic
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Pass-Transistor Logic
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Threshold Drops
VDD
VDD
PUN
S
D
VDD
D
S
0 ? VDD
0 ? VDD - VTn
VGS
VDD ? 0
PDN
VDD ? VTp
VGS
S
D
VDD
S
D
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Example AND Gate
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NMOS-Only Logic
3.0
In
Out
2.0
V
x

e
g
a
t
l
o
V
1.0
0.0
0
0.5
1
1.5
2
Time ns
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NMOS-only Switch
V
C
2.5 V
C
2.5

M
2
A
2.5 V
B
A
2.5 V
M
n
B
M
C
1
L
does not pull up to 2.5V, but 2.5V -
V
V
TN
B
Threshold voltage loss causes
static power consumption
NMOS has higher threshold than PMOS (body effect)
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NMOS Only Logic Level Restoring Transistor
V
DD
V
DD
Level Restorer
M
r
B
M
2
X
M
A
Out
n
M
1
Advantage Full Swing
Restorer adds capacitance, takes away pull down
current at X
Ratio problem
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Restorer Sizing
3.0

• Upper limit on restorer size
• Pass-transistor pull-downcan have several
  transistors in stack

W
/
L
1.75/0.25
V
r
e
W
/
L
1.50/0.25
g
r
a
t
l
o
V
W
/
L
1.25/0.25
W
/
L
1.0/0.25
r
r
Time ps
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Solution 2 Single Transistor Pass Gate with VT0
V
DD
V
DD
0V
2.5V
Out
0V
V
DD
2.5V
WATCH OUT FOR LEAKAGE CURRENTS
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Complementary Pass Transistor Logic
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Solution 3 Transmission Gate
C
C
A
A
B
B
C
C
C
2.5 V
A
2.5 V
B
C
L
C

0 V
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Resistance of Transmission Gate
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DESIGNING USING TG
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Transmission Gate XOR
B
B
M2
A
A
F
M1
M3/M4
B
B
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Delay in Transmission Gate Networks
m
R
R
R
eq
eq
eq
In
C
C
C
C
(c)
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Delay Optimization
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Transmission Gate Full Adder
Similar delays for sum and carry
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Dynamic Logic
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Dynamic CMOS

• In static circuits at every point in time (except
  when switching) the output is connected to either
  GND or VDD via a low resistance path.
• fan-in of n requires 2n (n N-type n P-type)
  devices
• Dynamic circuits rely on the temporary storage of
  signal values on the capacitance of high
  impedance nodes.
• requires on n 2 (n1 N-type 1 P-type)
  transistors

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Dynamic Gate
Mp
Clk
Out
In1
In2
PDN
In3
Me
Clk
Two phase operation Precharge (CLK 0)
Evaluate (CLK 1)
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Dynamic Gate
off
Mp
Clk
on
1
Out
In1
In2
PDN
In3
Me
Clk
off
on
Two phase operation Precharge (Clk 0)
Evaluate (Clk 1)
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Conditions on Output

• Once the output of a dynamic gate is discharged,
  it cannot be charged again until the next
  precharge operation.
• Inputs to the gate can make at most one
  transition during evaluation.
• Output can be in the high impedance state during
  and after evaluation (PDN off), state is stored
  on CL

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Properties of Dynamic Gates

• Logic function is implemented by the PDN only
• number of transistors is N 2 (versus 2N for
  static complementary CMOS)
• Full swing outputs (VOL GND and VOH VDD)
• Non-ratioed - sizing of the devices does not
  affect the logic levels
• Faster switching speeds
• reduced load capacitance due to lower input
  capacitance (Cin)
• reduced load capacitance due to smaller output
  loading (Cout)
• no Isc, so all the current provided by PDN goes
  into discharging CL

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Properties of Dynamic Gates

• Overall power dissipation usually higher than
  static CMOS
• no static current path ever exists between VDD
  and GND (including Psc)
• no glitching
• higher transition probabilities
• extra load on Clk
• PDN starts to work as soon as the input signals
  exceed VTn,
• Needs a precharge/evaluate clock

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Issues in Dynamic Design 1 Charge Leakage
CLK
Clk
Mp
Out
A
Evaluate
VOut
Clk
Me
Precharge
Leakage sources
Dominant component is subthreshold current
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Solution to Charge Leakage
Keeper
Clk
Mp
Mkp
A
Out
B
Clk
Me
Same approach as level restorer for
pass-transistor logic
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Issues in Dynamic Design 2 Charge Sharing
Charge stored originally on CL is redistributed
(shared) over CL and CA leading to reduced
robustness
Clk
Mp
Out
A
B0
Clk
Me
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Charge Sharing Example
Clk
Out
A
A
B
B
B
!B
C
C
Clk
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Charge Sharing
V
DD
M
Clk
p
Out
C
L
A
M
a
X
C
a

M
B
0
b
C
b
M
Clk
e
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Solution to Charge Redistribution
Clk
Clk
Mp
Mkp
Out
A
B
Clk
Me
Precharge internal nodes using a clock-driven
transistor (at the cost of increased area and
power)
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Issues in Dynamic Design 3 Backgate Coupling
Clk
Mp
Out1
1
Out2
0
In
A0
B0
Clk
Me
Dynamic NAND
Static NAND
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Backgate Coupling Effect
Out1
Voltage
Clk
Out2
In
Time, ns
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Issues in Dynamic Design 4 Clock Feedthrough
Coupling between Out and Clk input of the
precharge device due to the gate to drain
capacitance. So voltage of Out can rise above
VDD. The fast rising (and falling edges) of the
clock couple to Out.
Clk
Mp
Out
A
B
Clk
Me
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Clock Feedthrough
Clock feedthrough
Clk
Out
In1
In2
In3
In Clk
Voltage
In4
Out
Clk
Time, ns
Clock feedthrough
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Other Effects

• Capacitive coupling
• Substrate coupling
• Minority charge injection
• Supply noise (ground bounce)

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Cascading Dynamic Gates
V
Clk
Clk
Mp
Mp
Out2
Out1
In
Clk
Clk
Me
Me
t
Only 0 ? 1 transitions allowed at inputs!
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Domino Logic
Mp
Clk
Mkp
Mp
Clk
Out1
Out2
1 ? 1 1 ? 0
0 ? 0 0 ? 1
In1
In4
PDN
In2
PDN
In5
In3
Me
Clk
Me
Clk
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Why Domino?
Clk
Clk
Like falling dominos!
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Properties of Domino Logic

• Only non-inverting logic can be implemented
• Very high speed
• static inverter can be skewed, only L-H
  transition
• Input capacitance reduced smaller logical
  effort

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Designing with Domino Logic
V
V
DD
DD
V
DD
Clk
M
Clk
M
p
p
M
r
Out1
Out2
In
1
PDN
In
PDN
In
2
4
In
3
Can be eliminated!
M
Clk
M
Clk
e
e
Inputs 0 during precharge
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Footless Domino
The first gate in the chain needs a foot switch
otherwise second stage cannot prechargePrecharge
is rippling short-circuit current A solution is
to delay the clock for each stage
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Differential (Dual Rail) Domino
off
on
Clk
Mp
Clk
Mkp
Mkp
Mp
Out AB
Out AB
1 0
1 0
A
!A
!B
B
Me
Clk
Solves the problem of non-inverting logic
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Charge sharing problem
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Multiple output domino
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Compound domino
O1 A B C, O2 D E F and O3 G H,
O A B C D E F GH.
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np-CMOS
Me
Clk
Mp
Clk
Out1
1 ? 1 1 ? 0
In4
PUN
In1
In5
In2
PDN
0 ? 0 0 ? 1
In3
Out2 (to PDN)
Mp
Clk
Me
Clk
Only 0 ? 1 transitions allowed at inputs of PDN
Only 1 ? 0 transitions allowed at inputs of PUN
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NORA Logic
Me
Clk
Mp
Clk
Out1
1 ? 1 1 ? 0
In4
PUN
In1
In5
In2
PDN
0 ? 0 0 ? 1
In3
Out2 (to PDN)
Mp
Clk
Me
Clk
to other PDNs
to other PUNs
WARNING Very sensitive to noise!
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