SVT upgrade status

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SVT upgrade status A. Annovi - Assisi, 22
settembre 2004
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SVT Silicon Vertex Trigger
Finding tracks in the silicon
XFT tracks
SVX hits
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CDF DAQ Trigger
7.6 MHz Crossing rate
Detector Raw Data

• Level 1
• 7.6 MHz Synchromous Pipeline
• 5544 ns Latency
• 50 KHz accept rate

Level 1 pipeline 42 clock cycles
Level 1 Trigger

• 50 kHz accept rate

20 kHz actual
L1 Accept
SVT here

• Level 2
• Asynchronous 3 Stage Pipeline
• 20 ?s Latency
• 300 Hz accept rate

Level 2 Trigger
Level 2 buffer 4 events

• 20 ?s average Latency

35 ?s actual
L2 Accept
DAQ buffers
L3 Farm
To Mass Storage (50100 Hz)
Tails are important
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L1 accept rate is bottle neck

• L1A rate 20 kHz (vs 50kHz design)
• L1A rate limited by L2 exec time
• Rates at _at_ L100E30 (current luminosity)
• 15kHz high Pt L1A
• 15kHz TTT L1A (now PS 2)
• Rates growing quadratically with luminosity

Level 2 pipeline structure
Silicon readout
SVT processing
L2 decision processing
Optimized but slower than design
Upgrade in progress
Upgrade in progress
SVT upgrade has large impact on maximum L1A rate!
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Tempi di processamento come agisce lupgrade ?
SVT exec time proporzionale candidati da
fittare

• Ricetta per velocizzare il tempo di esecuzione di
  SVT
• pattern piu sottili (AM grande) ? meno fits.
• Road Warrior per rimuovere i ghosts

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TEMPI DI REALIZZAZIONE

• Nuova AM-board inizio estate 2004 (Pisa)
• durante estate 2004 test con FPGA (Pisa)
• Progetto prototipo AM-chip luglio 2004
  (Ferrara-Pisa)
• consegna chip 2 mesi disponibile ad ottobre.
• Nuova LAMB montare nuovo AM-chip a ottobre 2004
  (Pisa)
• test del chip scheda ottobre dicembre 2004
  (Pisa-Ferrara)
• produzione inizio 2005 (Pisa-Ferrara)
• installazione estate 2005 (Pisa-Ferrara)
• Altri DAQ/Trigger upgrade previsti nel 2006

Road Warrior . . . (60 k
Fermilab) messa in opera entro fine 2003 ? F.
Spinella (in funzione)
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Tsukuba Chicago
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Pulsar (Pulser And Recorder) Design
AUX card
Custom Mezzanine
Mezzanine slots
Pulsar
Works up to 100MHz
Top view
Three ALTERA APEX 20K400 FPGAs
Bottom view

• I/O Mezzanine cards for
• S-LINK (CERN/LHC)
• Hotlink
• TAXI
• to be specified

• Self-testable
• Modular, lego-style open design
• Replacing gt 10 CDF board types
• all CDF, many ATLAS connectors/standards

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AMchip
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What are we doing?

• AM (A. Annovi, A. Bardi, M. DellOrso, P.
  Giannetti, P. Giovacchini, I. Roffilli, F.
  Spinella, R. Tripiccione)
• new AMchip (Pisa and Ferrara)
• new AMplug (LAMB)
• new AMBoard (AM)
• RW installed and working!!!
• AMS/RW (Piendibene M. and Spinella F.)
• AMS firmware
• RW firmware

3 test stands
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AMchip status .

• 200 dies produced (expected 80)
• 150 packaged chips by September 30
• Testing the Test stand hw/sw with FPGA
• Automatic test vector transfer from simulation
• Test stand working

Inputs from Pattern Generator
Output to Logic Analyzer
AMChip socket
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LAMB status
FTK LAMB prototype now used for sw development
SVT LAMB prototype v1 mounting 4/32 FPGAs some
mounting problems CLPDs/FPGAs programmed Tests in
progress
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AM status
1st crate FTK AM prototype with FTK LAMB for sw
devel and/or with SVT LAMB for LAMB test
2nd crate SVT AM prototype Mounting
delays talking with AMS/RW in pulsar (starting
now)
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AMS/RW status
DATA IO1 firmware ready for test stand
CTRL firmware partial version for test with AM
in progress
DATA IO2 firmware (RW function) to be done
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• Year chip boards devel. Total
• 2003? 120 kE 10 kE (test b.) 5 kE 135
  kE
• - 10 kE (protot.) 30 kE 40
  kE
• 53 kE 100 kE (produc.)
  153 k
• 40 kE 40 kE
• Ferrara Pisa
• Le Pulsar sono pagate dagli USA
• totale secondo upgrade 280

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Conclusions
Hardware and firmware development on
schedule. Most of the fun (or pain?) will start
soon standard cell AMchip by September 30
LAMB and AM in test stand now
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Backup slides
SVT
backup slides
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Trigger/DAQ Upgrades for Run IIb

• Need to Maintain or increase bandwidth
• ?Luminosity ? ? Rate (sL)
• ?Luminosity ? ?inter/x-ing
  ? ?Complexity (and fakes) ?
  ?Event Size, ?Exec. time
• All ?sphysics to tape
• L1 Bandwidth (output to L2)
• XFT ??Purity ??strigger(L1, L2)
• SVT, L2 ??L2 Exec. t ??L1 Bandwidth
• L2 Bandwidth (output to L3)
• COT TDC ??Readout rate
• Level 3 Processing ??L3 Exec. t
• Event Builder ??Readout rate
• L3 Bandwidth (output to tape)
• CSL ??Tape rate (not under IIb project)

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AMB autumn 2004
Prototype tests in Pisa 2nd prototype generation
AMB during 2005
AMB the group will split between Pisa and
Fermilab the first six months. Pisa Bardi,
Giannetti January-May production of amchips,
LAMBs and AMBoards Fermilab P. Giovacchini,
A. Annovi January-May (a) tests of the AMB
prototype with all procedures (b) insert AMB
in Run Control June-September all in
Fermilab install and test of the whole system
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SVT performances
IP resolution
From TDR sd25mm
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Pisa Annovi dottorando Bardi ingegnere -
art. 23 DellOrso prof. Associato
Giannetti dirigente di ricerca Spinella
assegnista INFN P. Giovacchini laureando
M. Piendibene borsista Ferrara Damiani
assegnista (10) Sartori assegnista (50) Tri
piccione prof. Ordinario (10) Cotta tecnologo (
10) Chiozzi tecnico (20) I. Roffilli
contratto
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Software TODO list

• Online (11 mesi FTE)
• DAQ related code
• Diagnostic
• Spy monitoring
• HW Diagnostic/debugging tools
• Offline (4 mesi FTE)
• Configuration
• Simulation
• Diagnostic on data

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sw