TGC Electronics mtg ROD

1
TGC Electronics mtg ROD-

• S.Komatsu
• Tokyo Metropolitan University

2
Contents of ROD Board
3
Photograph of ROD
4
Device Capability

• SH4 CPU 167MHz
• Cache 8kB x 2
• FIFO width 36bit depth 32k
• Flash RAM 5kB
• SDRAM 128MB
• DPRAM 128kB

5
Procedure of Operation
6
Contents of DAQ Program

• Flag Check for all Glink FIFO
• (EMPTY, Almost FULL, FULL)
• Read and Check for all Glink FIFO
• (Header, Data, Trailer)
• (Data not change)
• Write to OutFIFO (VMEFIFO or ReadOut FIFO)
• (ROB format Header, Data, Trailer)

7
Test Method

• Using Test Write Mode, we tested 13 channel
  input.
• Test Write Mode
• 1. Test Data is written in Glink FIFO
  from SH4.
• 2. DAQ program is made to run.

8
Performance

• Operation is dependent on the number of accesses
  of internal bus
• Time concerning one bus access about 200ns
• 13ch no hit
• 3LW Header and 1LW Trailer about 14us
• 13ch all hit
• 3LW Header and 1LW Data and 1LW Trailer
• about 20us

9
Countermeasure

• The number of input channel is lessened
• 1ROD/Octant gt 2ROD or 3ROD/Octant
• Data format size sent is made small
• ex. If no hit gt header decrease
• 4LW gt 1LW
• 13ch no hit
• 1LW Header from SSW about 7us
• the average estimated from TDR
• 4ch hit 9ch no hit about 11us

SSW Header
SLB Header
SSW Header
SLB Header
SSW Trailer
10
Countermeasure

• Increase in efficiency of DAQ program
• Bus access time is made quick
• gt Modify VHDL code of FPGA
• Change microcomputer
• gt faster CPU microcomputer or DSP