CS M51A/EE M16 Winter

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CS M51A/EE M16 Winter05 Section 1 Logic Design
of Digital SystemsLecture 11
February 23

• Yutao He
• yutao_at_cs.ucla.edu
• 4532B Boelter Hall
• http//courseweb.seas.ucla.edu/classView.php?term
  05Wsrs187154200

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Outline

• Administrative Matters
• Chapter 7
• Specification of Sequential Systems
• State Minimization

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Administrative Matters

• Project 2
• Is posted on the web
• Due on March 2 (Wednesday)
• Teamwork is allowed and encouraged
• Find your partner as early as possible
• Homework 7
• Is posted on the web
• Midterm
• Will be handed back and discussed on Next Monday

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Sequential Systems Overview

• Basic Concepts
• Synchronous sequential systems
• Clocks
• States
• Finite state machines
• Mealy and Moore machines
• Specification
• Time behavior (I/O sequence)
• State transition table
• State diagram
• Minimization

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Definition of Sequential Systems
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Sync. Vs. Async. Sequential Systems
Synchronous
Asynchronous
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Clock

• An independent periodic reference signal
• Provided by
• An internal crystal
• An external 60 Hz alternating current
• Make sure you know
• When is the present (t)
• When is the next (t1)
• back to the future
• When is the previous (t-1)
• forth to the past

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Time-Behavior Specification

• Behavior of a sequential system can be specified
  by a sequence of input(s)/output(s) pairs with
  respect to the clock signal

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Example 7.1 Serial Decimal Adder

• Addition is performed one digit at a time,
  starting from the LSB
• Output is generated at each time instant
• As a result, a 8-digit serial decimal adder needs
  8 clock cycles to finish the calculation

s x y 2163875373652425
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State

• Introduced to help memorize the complete
  input/output sequences
• Usually number of states are finite
• Itself is also a time function
• Two types of states are defined
• present state (PS) s(t)
• next state (NS) s(t1)

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State Description of Sequential Systems

• A sequential system can be specified as a finite
  state machine (FSM) by specifying
• output function z(t) H(s(t),
  x(t))
• state transition function s(t1) G (s(t), x(t))

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Example 7.3 - Serial Decimal Adder

• Inputs x(t), y(t) ? 0,1, , 9
• Outputs z(t) ? 0, 1, , 9
• State c(t) ? 0, 1
• Initial State c(0) 0
• Functions
• State transition function c(t1)
• Output function z(t) (x(t)y(t)c(t)) mod 10

1 if x(t)y(t)c(t) ? 10 0 otherwise
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State Transition Table

• An extended truth table for specifying output
  function and state transition function in a
  tabular form

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Example 7.4 Odd/Even Detector
Given a system whose input has two values a and
b, and whose output also has two values, 0 and 1.
The output at time t is 1 if the number of bs in
the input x(0,t) is even, and 0 otherwise.

• Inputs x(t) ? a,b
• Outputs z(t) ? 0, 1
• State s(t) ? Even, Odd
• Initial State s(0) Even

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State Diagram

• A graphical specification of a sequential system

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Example State Diagram
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Mealy and Moore Machines

• Mealy Machine
• Its output depends upon both input and state
• Moore Machine
• Its output depends only upon present state

Mealy Machine
Moore Machine
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Example 7.5 - A Moore Machine
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How to Select State Names

• Use integers as state names
• Example A modulo-64 counter
• Input x(t) ? 0,1
• Output z(t) ? 0,1,,63
• State s(t) ? 0,1,,63
• Initial State s(0) 0
• Function
• Transition function s(t1) s(t)x(t) mod 64
• Output function z(t) s(t)

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How to Select State Names (Contd)

• Use state-vector approach
• state is represented by a vector s (sn-1, , s
  0)
• Example
• A sequential system that counts the occurrence of
  55 different events. When the count of event I is
  a multiple of 100, the output is z(t) i,
  otherwise, z(t) 0
• Input x(t) ? 1, 2, , 55
• Output z(t) ? 0, 1, 2, , 55
• State s(t) (s55,,s1), si ? 0,1,,99
• State s(0) (0,0,,0)
• Functions
• Transition function si(t1)
• Output function z(t)

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Case Study 1 Finite Memory Systems

• A sequential system has finite memory of length m
  is z(t) depends only on the last m input values
• z(t) F(x(t-m1), t))
• Example 7.12
• z(t)
• Finite memory of length four
• All finite-memory machines are FSMs
• Not all FSMs are finite-memory
• z(t)

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Case Study 2 Pattern Detector

• Detect sub-patterns in the input sequence
• Two types
• overlapped and non-overlapped
• Example
• Input x(t) ? 0,1
• Output z(t) ? 0,1
• Function z(t)

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Case Study 3 Controller

• A FSM that produces control signals as the states
  are traversed.
• Control signals determine actions performed by
  other parts of the system.
• Two types
• Autonomous
• State transitions follow a fixed sequence of
  states, independent of any inputs except the
  clock.
• Non-autonomous
• The transition is decided by external inputs

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Vending Machine Controller
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Vending Machine Controller (Contd)
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State Minimization

• Motivation
• High-level design may generate many redundant
  states
• Fewer states may mean fewer state variables
• To reduce the complexity and cost
• Basic concept
• Two states are equivalent if they are impossible
  to distinguish from the outputs of the FSM, i.
  e., for any input sequence the outputs are the
  same
• (1) Output must be the same in both states
• (2) Must transition to equivalent states for all
  input combinations
• Basic Methods
• Table matching
• Implication Chart

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Table Matching Procedure - Overview

• Starting with the state table
• Step 1 Row matching with respect to outputs
• Step 2 Rename the newly partitioned classes
• Step 3 List their next state transitions by
  using new names
• Step 4 Check if partitions are same by column
  matching within classes
• If no, go back to Step 1
• If yes, The states are minimal
• Write the state table for the minimal states

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State Minimization - Example 7.14
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Example 7.14 (Contd)

• Row Matching
• P1 (A, C, E) (B, D, F)
• Column Matching

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Example 7.14 (Contd)

• Row Matching
• P2 (A, C, E) (B, D) (F)
• Column Matching

• Row Matching
• P3 (A, C) (E) (B, D) (F)
• Column Matching

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Example 7.14 (Contd)

• Column Matching
• P4 (A, C) (E) (B, D) (F) P3
• Stop The states are minimal

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Summary

• Specification of sequential systems
• time-behavior
• state-transition table
• equation
• state diagram
• Several common types of sequential systems
• pattern detectors
• controller
• State Minimization

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Next Lecture

• Chapter 8 Sections 8.1-8.7