Interrupts on the Intel 8051

1
Interrupts on the Intel 8051

• Presented by Joe Conner
• For Advanced Embedded Systems DesignBAE 5030
• 08/30/04

2
Overview

• Memory Map
• Interrupts
• How interrupts are handled
• Response Time

3
Memory Map

• TCON (0x88)

• IE (0xA8)

• IP (0xB8)

• SCON (0x98)

4
Interrupts

• The 8051 provides 5 interrupt sources
• INT0
• INT1
• TF0
• TF1
• RI/TI

External Interrupts and can be either level or
transition activated
Timer 0 and 1 overflow/rollover activated
Serial Port both receive and transmit Since both
TX and RX are the same interrupt, the service
routine will have to determine which it was.
All the bits that generate interrupts can be set
or cleared by software, with the same results as
if they had been set or cleared by hardware.
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InterruptsFlags
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InterruptsEnabled and Disabled

• All interrupt sources can be individually enabled
  or disabled by setting bits in Special Function
  Register IE

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How Interrupts are Handled

• Interrupts flags are sample at S5P2 of every
  machine cycle.
• The 8051 then generates a call (LCALL) to the
  corresponding interrupt service routine provided
  one of the following conditions is NOT meet.
• An interrupt of equal or higher priority is
  already in progress
• The current instruction is not yet complete
• The instruction in progress is RETI or any write
  to the IE or IP registers

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How Interrupts are Handled

• Priority can be set by the software
• All interrupts can either be set to a high or low
  priority
• Priority works as follows
• High-priority interrupts can not be interrupted
• Low-priority interrupts can be interrupted ONLY
  by high-priority interrupts
• If two request of different priorities occur
  simultaneously, the request with the higher
  priority is serviced.
• If request with the same priority occur
  simultaneously, then an internal polling
  sequence is used

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How Interrupts are Handled

• If none of the previous conditions have violated,
  then the 8051 will generate a LCALL to the
  appropriate serving routine. In most cases it
  also clears the flag that generated the
  interrupt.
• Note Serial Port flag is never cleared and as
  such must be handled by software
• LCALL pushes the current contents of the Program
  Counter onto the stack and reloads an address
  that depends on the source of the interrupt

• Execution proceeds until RETI is encountered. The
  execution of this command allows the 8051 to know
  that the current interrupt routine is no longer
  in progress
• The 8051 then reloads the Program Counter from
  the stack and continues from where is left off.

10
Response Time

• In a single-interrupt system, the response time
  is always more then 3 cycles, but less then 9
  cycles.